FPGA Compile Error: Timing Violation

[tiba.shokatpour@gmail.com]

Hi

I have a simple FPGA program that compiles in cRIO without any problems, but I want to use the FPGA program on the NI 9144 EtherCAT Expansion Chassis in FPGA mode to NI PXIe 8135 (Code file attached). As you know there are some differences between programming the local FPGA and the FPGA for EtherCAT RIO, that must be used user-defined I/O variables (this paper).

For Compiling I did step by step as this paper said, we get successful processes, but after file generation complete we have an error (that attached). It shows that the file can not run in chassis. 

Please help me.

[tiba.shokatpour@gmail.com]

Hi

I found the solution for Timing Violation Errors, In this link ( section 4)

The following are suggestions for improving timing in your FPGA code:

• Adjust the build settings to optimize for performance (Note: this may increase compilation times, and may result in area trade-offs).
• Optimize your code. Try the following best practices and optimization techniques within your LabVIEW FPGA code.
  • Reduce the amount of logic in the VI
  • Add pipelining to increase parallelism
  • Use Timed Loops instead of other loops
  • Change arbitration settings

I just use Timed Loops instead of other loops, so the compilation runs successfully.  

Regards.