FPGA Compile server cache (Vivado)

[Intaris]

In the past, the FPGA cloud compiles were massively accelerated by enabling caching on the server of any Xilinx IP.  This led to a huge improvement in the usability of the cloud compile.  That was way back. Using ISE.

Now I am compiling with Vivado and I am running into a different problem.  We use a lot of small Block RAMs and about a dozen other Xilinx IPs.  These are instantiated in code (not in the project) and each and every time we start a cloud compile, it needs to re-create the Xilinx IP for each and every one. This takes about 5.5 hours. then the compilation is finished in 40 minutes.

This is absolutely killing my workflow. Could it be that the FPGA compile servers are not caching Xilinx IP cores for Vivado compiles?

No cached IP found!!

I attach an image of a Compare between a local compile (Top) and a cloud compile (bottom). Note that the local compile recognises that the Xilinx code has already been created before and uses the cache whereas the cloud compile does not. The Green highlighted text is text included in the cloud compile log which simply does not exist in the local compile log (it documents the creation of the Xilinx IP). Note also that this compilation has been performed many times in the cloud, there should certainly be cached information there.  It seems that there are no checkpoints for any of our Xilinx IP on the cloud compile server.  This is really disappointing. It makes the cloud compile essentially useless for our design.