FPGA - Compile timing error - on board clock lower than requested clock

[truby]

I'm having trouble compiling my FPGA code. The problem is the clock on my FPGA target is lower than what I am able to select when creating my code. This causes me to get a timing error when compiling. I've posted pictures to try to help. Does anyone have an idea on how to fix this? FWI I'm very new to LabVIEW.

[GerdW]

Hi truby,

Does anyone have an idea on how to fix this?

Well: improve your code!

Don't you think it would help to see your FPGA VI (even better the whole project)?

How else can we tell how to spot the problem and how to get away with it?

Did you try to compile with speed optimization enabled (in the compile settings)?

Do you use a TWL in your code with too much (unoptimized) code inside?

[truby · Accepted solution]

Thanks for the reply. I found out I was given faulty code. I was given something and told to build on top of it. Now the original code has been fixed and its working. I thought that this error could of been a common LabVIEW error and not a problem with the code.