LabVIEW
FPGA: Compiled w/ 14.4, Fails w/ Vivado 2013.4
Solved!
My FPGA code, which compiled fine in LV 2011, then in LV 2013 (using Xilinx 14.4). I have not had to touch in quite a while....
Upgrading to LV 2014 SP1, I find I must re-compile to get the bit file to run on the cRIO Target. However, now it does not compile. Cloud compiler reports timing error. Cloud compiler (and local compiler for that matter) report using Vivado 2013.4
The code handles a 9205 C series analog input moudle. 6 of the 32 channels are run through an RMS calculation. A while loop is set to do this every 185 uSec (9205 card channels = 4uSec minimum update * 32 channels = 128uS = theoretical maximum to run the FPGA and get valid data). Every 650 samples a new RMS value is computed.
The rest of the channels get averaged, 8 samples are averaged every 100th iteration of the above loop.
The timing for the loop comes from a front panel control. I have tried increasing this from 185 to 200 uSec but it does not help. All input and output to the FPGA VI are written to / read from the real time host *(cRIO-9068) be using the front panel controls.
This code has not changed in a great long while. I could share it if it would help.
My questions center around the investigate timing results window. Nothing here seems helpful. What is 'path 1' and how does it relate to the block diagram? Show element and show path are inhibited. I have tried changing the build - optimize for performance, and optimize for area etc... but compile still fails.
I will be creating a ticket with NI. But thought pehaps someone here might have additional insight.
