FPGA DMA FIFO multiple host

[carlos_camargo]

Is it explained somewhere why it is that I can only write an FPGA DMA FIFO from a single host?  Both hosts pull up a reference to the FPGA bitfile with no problem, and can read a different FIFO.  If I write to a DMA FIFO from one host, that works ok, but whenever I write from a second host, I get the error -63082: The operation could not complete because another session is accessing the FIFO.  Close the session and retry.

The thing is that both Hosts weren't attempting a write at the same time, one had written to FIFO and finished writing.  The other began to write well after the first completed.

Is there a way to make this work?  If not, that is ok, I programmed around it.  I would like to know though, why this happens.

[Terry_ALE]

Can you change the software architecture to send everything from one place?  I almost would never recommend writing to a DMA-FIFO from more than one place on the Host (or even the FPGA going the other way).

[carlos_camargo]

I have already changed my architecture to a method where each host writes to an array (with handshaking to assure data transfer integrity) in the FPGA.  Your suggestion would have required all that handshaking plus transferring from there to the FIFO.  It's not a bad way to go, I briefly considered it, but I figured in the end that would just add more code for no real value.

My question has more to do with why the error occurs.  Using a FIFO is sweet and slick, not being able to write from multiple hosts is bothersome.  I want to know the technical reason that isn't possible.

[Terry_ALE]

I do not know the technical reason that you are getting an error.  I suggest making a simple example that writes to the DMA-FIFO from more than one place.

Once simple reason for avoiding this approach is performance.  When the application requires say read/write from/to disk and we end up using E-DVRs I assume multi-hosts would not perform as expected.

Another would be the chance of a race condition.  How does the FPGA know which host's data it is getting?

In the end an FPGA is another instrument.  I would not write or read to/from a DAQ card from more than one place.  The same applies to an FPGA based instrument.

[carlos_camargo]

Yeah, I'm mostly curious about the source of the technical limitation.  I did make a simple example that wrote to the DMA FIFO from more than one host.  The error occurs as soon as a write is attempted from the second host attempting a write, regardless of the order in which the hosts opened a reference to the FPGA.

My application wasn't performance intensive, the hosts have to take turns writing to the DMA FIFO because they respond to each other.  So, there's zero chance of overlap in writing to the DMA FIFO.

The FPGA knows which host is send it data by sending a two byte data, one of the bytes contains a value indicating the host that sent the data.

Your application didn't need the feature of writes from multiple hosts, mine did.  The reason I wanted to share the FIFO was that my particular hardware has a maximum of 3 DMA FIFO's available.  It would have been great if I had endless FIFO's (or at least four) to work with.  If I had more time, I might have been able to rewrite my application to have a single host doing all the work but that would have resulted in much more code in a single top-level VI, the current separation is much more intuitive.

[Terry_ALE]

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@carlos_camargo wrote:

I did make a simple example that wrote to the DMA FIFO from more than one host.  The error occurs as soon as a write is attempted from the second host attempting a write, regardless of the order in which the hosts opened a reference to the FPGA.

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Given your simple test, I think you will have to change your code to have only one interface to the DMA-FIFO.

DMA stands for direct memory access which could allow us to make guesses based on the term and your results above.  You could email NI support for more details on the technology.  Sorry I could not be more helpful.

[carlos_camargo]

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@Terry_ALE wrote:

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Given your simple test, I think you will have to change your code to have only one interface to the DMA-FIFO.

DMA stands for direct memory access which could allow us to make guesses based on the term and your results above.  You could email NI support for more details on the technology.  Sorry I could not be more helpful.

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Thanks for trying to help me.  I switched to transferring data via shared variables (arrays of 8U for data, and booleans for handshaking).  This works fine for me as my data is finite in size and small enough to fit on the FPGA.

Do you know why such large FIFO's can fit on FPGA (for example I can fit several 32U 1,024 element FIFOs), but arrays barely fit (2 8U 200 element arrays couldn't fit)?

BTW: your book looks very interesting, I'm going to see if I can my work library to get a copy or two.  Maybe my department next year as well.

[Terry_ALE]

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@carlos_camargo wrote:

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@Terry_ALE wrote:

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Given your simple test, I think you will have to change your code to have only one interface to the DMA-FIFO.

DMA stands for direct memory access which could allow us to make guesses based on the term and your results above.  You could email NI support for more details on the technology.  Sorry I could not be more helpful.

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Thanks for trying to help me.  I switched to transferring data via shared variables (arrays of 8U for data, and booleans for handshaking).  This works fine for me as my data is finite in size and small enough to fit on the FPGA.

Do you know why such large FIFO's can fit on FPGA (for example I can fit several 32U 1,024 element FIFOs), but arrays barely fit (2 8U 200 element arrays couldn't fit)?

BTW: your book looks very interesting, I'm going to see if I can my work library to get a copy or two.  Maybe my department next year as well.

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Space is one aspect of making an FPGA compile succeed; routing and timing are other factors.  Also, DMA-FIFOs are always with block memory where the array may be set to Auto implementation.  If you right-click on the array properties you should see this setting.  This is only for constants.