FPGA DMA FIFO - "Timed Out" question

[tartan5]

Hello All,

I've got a DMA FIFO (Target to host) set up on a PXI-7811R FPGA card.  The buffer size is set to 1023.  I have a FIFO write set up inside a single-cycle timed loop, with the timeout wired with 0.

This will be used in a Target to Host configuration, but I wanted to test the FPGA code by itself, so I'm running from the FPGA UI.  I set the number of acquisitions to 5000, expecting to see the "timed out" flag get asserted, which it appears it did not.  I have a shift register set up cycling through my single-cycle loop, I OR the timed-out flag with the shift register, so any time-outs should set this flag and it will stay set until I clear it.

Does the "timed out" flag only function after the DMA synchronization has begun between the host and target?  Or should it be working now?

Thanks!

[Brian_R]

The "Timed out?" flag becomes valid immediately when the FPGA begins running.  The attached code will stop running when trying to insert the 1024th element.  Additionally, the DMA FIFO will remain full in between runs - it will have to be cleared by the host in order to run again.  So the first time the code runs, the output will be 1023, the second time, it will be 0.

Message Edited by Brian R on 09-20-2007 06:38 PM