02-22-2013 04:23 AM
Just a quick question...
Are there limitationsa s to what we can call a Target to Host FIFO on an FPGA target?
I was testing code and when I had a ":" in the name it wouldn't work. Now I've removed the ":" (nice long compilation of course) and now it seems to work......
Are there name limitations for DMA FIFOs?
Shane.
02-22-2013 08:23 AM
Intaris,
I'm sure there are limitations. I've never seen a list. I would think that most of the limitiations are directly related to the Xilinx compilers and VHDL. I know that ':' is a character is used as part of the VHDL syntax.
02-22-2013 10:43 AM
Really, ":" is part of the VHDL syntax.
That would explain a lot.
Still lost two days over it though. One thing's for sure. I'll never forget that piece of information again.
Shane.
02-22-2013 11:31 AM
Hi Shane,
Was this in 2012? I'll file a bug report if so...