FPGA: Delay on digital input

[M.haefner]

Hi,

I've experienced a strange behaviour when reading a digital input of my PCI-7833 FPGA device: What I want to do is to trigger an output on the falling edge of a digital input. To do so I implemented a SCL in which I compare the readings from current and the preceeding loop iterations and trigger the output if the desired transition occured (like in fig.12 http://zone.ni.com/devzone/cda/tut/p/id/2993). The problem is that I get quiet long delays between the transition at the input and the change of the output. Furthermore the delay is not a constant number of clock cylces. I tried different loop rates for the SCL and got the following results: 20MHz -> 210ns delay, 40MHz -> 136ns, 80MHz -> 100ns, 120MHz ->  74ns. Can anybody explain that behaviour or even tell me how to solve that problem?

Thanks,
Matthias

[mal11]

are you sending data back to a Front-Panel on the VI??

[temin_fpga]

Hi

iam using 9004 compact rio controller with NI 9201 analog input module and NI 9401 digital module installed in it.

iam able to receive the analog input from a temperature sensor connected to AIO. if the value crosses a threshold ,i want  to trigger the DIO 0 ,by which i should turn ON a relay and tthus turn ON a cooling fan. i couldn't trigger the digital output by connecting a boolean control ,even if the control is high i am unable to get the output(5v) at the DIO 0 pin.  

plz  tell me what to do.. 

[temin_fpga]

this is the image of my vi. 

[M.haefner]

Hi,

have you configured the IOs as output with the "invoke method" primitive? They are inputs by default.

Matthias

[temin_fpga]

thanks for the reply,

    to make it simpler i created a new project and i dragged and dropped DIO 0 from the project explorer to the block diagram of fpga vi (inside a while loop)

right clk the i/o node and changed the option from read to change to write... gave a boolean control as input. compiled and run it.. still when i give boolean true as input i couldn'd get the output

do i have to do any other thing..if so kindly attach a image file of what i have to do..

[M.haefner]

Hi,

I've just checked the available settings for the 9401 IO-Module. In the project explorer you have to right-click the IO-Module and select the properties entry. Here you can switch between input and output.

Regards,

Matthias

[temin_fpga]

thanks haefner for your reply, it worked. the options for changing is from DIO7:4 & DIO3:0 ie., the 8 DIO is divided into two sets and each can be configured for input or output. 

since iam a beginner kindly answer my following doubts:

-> why can't we individually assign each pin as input or output

->whenever i compile and run the FPGA vi(created under FPGA target in project explorer) and then deploy the host vi(created under crio), it won't deploy successfully, it gives me a communication error,if i click ok then another window will pop up saying "warning:connection with the real time controller has been lost" again if i click ok and deploy again it is successful.why it fails the first time?

     kindly reply

Regards,

temin

[M.haefner]

Temin,

I'm happy that I could help you.

Regarding your further questions:

In what way the DIOs can be switch between input and output depends on how the IOs are realised in hardware. I guess the limitation is due to minimizing complexity and costs of the IO-Modul. In principle it should be possible to have an IO-Modul with IOs that can be switched individually between input and output. But I don't have much experience with CRIO. I work with R-Series and FlexRio Boards. There you can switch each IO individually, even at runtime.

Since I don't work with CRIO I cannot help you with your deployment problem - sorry.

Regards,
Matthias