FPGA Digital Signal Output Problem

[bugsmashers]

Hi,

I am having a problem outputting a signal through my PCI-7831 and would appreciate any advice anyone has as I am beginning to crack the wall where I am banging my head into it. 

My software is LV7.1 with FPGA module 1.1.  I am controlling a VI compiled onto the PCI-7831 with a host VI in windows.  I am viewing the outputs I mention on a high end oscilloscope.  I'm relatively new to LV and very new to the FPGA module.

The FPGA VI consists of 3 while loops though only 2 loops are not performing as expected.  The FPGA while loops in question contain a single sequence structure that has as their first frames an IRQ 0 and 1 respectively . 

In the host VI I am waiting for IRQ, writing the value of 2 wait timers,  and acknowledging the IRQ in the first frame of a sequence.  The FPGA then sets the states of 2 DIO outputs to both high.  Then the timers keep both outputs high until the next frame is reached, then 1,0 is written, the second wait expires, and the loop repeats until the while loop conditions in the host VI are met and the sequence in the host VI indexes (this is about 1 second.)

For the second loop, I am going to the next frame in the host VI. This host works the same as the above sequence but only 1 value is being written, 0,1.

In any case, it works but has 2 bugs I can't reason.

The last, and only the last, iteration of the "both high" period is wrong.  The 1,1 becomes 1,1, then 0,1 about halfway through the wait, then the 1,0 occurs properly, then the 0,1 period begins properly.

The other bug is that at the beginning of the 1,1; 1,0 sequence the 1,0 is repeated twice.

I am using these signals to control a custom high amplitude bipolar digital signal generator.

I have posted my VI's if anyone would like to see them.

Thanks,

Ben

Message Edited by bugsmashers on 07-21-2005 12:57 PM

Message Edited by bugsmashers on 07-21-2005 12:58 PM

[Dustin_W]

Hi Ben-

I took a look at your code, and I can explain the first error you are talking about, but I don't think I understand the second error.  For the first error, lets start on the last iteration of the first while loop in your host code.  It first waits on IRQ 0, then sets the 'high' and 'low' parameters on RT, then acknowledges IRQ 0.  At this point on the FPGA side, the top loop (1,1 loop) begins to execute and sets the lines to 1,1.  Meanwhile back on the host, your first loop completes and the second loop starts.  The first thing the second loop does is wait on IRQ 1.  It doesn't have to wait at all because IRQ 1 was set long ago when the FPGA program started, so it clears IRQ 1, and the second FPGA Loop immediately sets the lines to 0,1.  The next thing that happens is your top loop in FPGA (1,1 loop) finishes waiting for the time specified in 'high' and moves to the next sequence frame and sets the lines to 1,0, next the second loop finishes its wait ('Wait Zero') starts the loop over again, sends IRQ 1, which is handled by your second host loop, it acknowledges IRQ 1, and then your second FPGA loop sets the lines back to 0,1.  Long explanation, but I hope not too confusing.  Synchronizing the host and FPGA with everything happening in parallel can get to be a lot to wrap your brain around.

One comment on the code - From your description and looking at the code it looks like the first pulse iterates for a given period of time, then the second.  The way you have it written right now the pulse period will not be very deterministic - especially if you are using windows as your host.  The reason is that every iteration of the pulse depends on an IRQ interaction, which means you are waiting on your host CPU to do something.  Granted, the host should react quickly, but it is not deterministic - if windows is your host, and you start dragging windows around, you'll notice your period become longer than 'high'+'low'.  A better architecture might be to send the number of iterates of the 1,1 - 1,0 loop you want to execute down to FPGA, and let FPGA count the iterations and report back when it's done.  Then start the second loop, or send all the info down to FPGA and let it control both loops.  If setting 'high', 'low', and 'wait zero' need to happen through out, use the read/write control to just update those on the fly from the host rather than making the FPGA halt while they are updated.  If determinism on the period length is not important for your code, or you designed it the way you did for other reasons, then ignore everything I just said .

Good luck, sorry I couldn't help on the second problem, if it's still an issue, post back with a little more detail on what '1,0 is repeated twice' means

Dustin

[bugsmashers]

Hi,

I was able to get it fixed up.  This signal doesn't need to be deterministic as the signal itis generating has a very wide tolerance, but it is very important for upper level VI's (not yet written) to be able to control the period. 

Thanks for the help.

Ben