FPGA: Does priority have an meaning with FPGA-running VI?

[itayshom]

Hello,

I am using NI-7833R FPGA. I added some code containing single-cycle timed-loop to an already existing VI. However the VI won't compile because its priority was "time-critical priority (highest)", and single-cycle timed loops aren't allowed in such VIs.

When lowering the VI execution priority, is does compile.

My question is: Does the execution priority matter in FPGA target VIs? This is very strange since these VIs execute independently without any threading issues (AFAIK).

Is there a cause for concern if I lower the priority from critical?

Thank you,

Itay.

[crossrulz]

In FPGA, it is all hardware.  So there really is no such thing as priority.  Being inside of a SCTL, everything should complete within a single clock cycle.