FPGA FIFO Real Time Error -61206

[nslogan]

I used this white paper as a basis for my code. My FPGA look like:

And my Real Time (RT):

I'm using a cRIO-9022 and currently just trying to get the groundwork layed for my project. The problem is that the FPGA side runs fine but the RT environment runs for maybe 2 or 3 seconds and close with this error:

Code: -61206

Source: Read/Write Control in FIFO_pressure_RT.vi

I haven't dealt with the FIFOs in LabView before so I have no idea what's causing this. Any ideas?

Thanks,

Logan

[cirrusio]

Logan,

How is your Open FPGA Reference configured?  By VI?  By bitfile?  Where is the error first being thrown?  How do you know that the FPGA is running ok?  Are you sure that it is running for 2 or 3 s or is it getting hung up on one of the read/write nodes searching for the reference?  Is your FIFO on the FPGA properly scoped (I believe it should be target scoped and not any kind of DMA)?

Cheers, Matt

[nslogan]

Hey thanks for the reply, sorry I'm new to this whole thing so I wasn't sure what details I should include.

• How is your Open FPGA Reference configured?

By VI

• Where is the error first being thrown?

I rewired my error indicator and tracked the error to the read block

This is where it happens, same error. Also of note, the value x/y stays the same for the duration of the run.

• How do you know that the FPGA is running ok?

It seems to be running ok when observing the front panel, I'm honestly not sure what I would need to check on that to confirm. The analog value (Input Data (Synchronous Display)) is operating properly.

• Is your FIFO on the FPGA properly scoped?

It's target scoped and otherwise configured exactly the same as that white paper.

Let me know if there's anything else you need to know about it!

Thanks

[cirrusio]

Logan,

What happens when you configure by bitfile reference?  I suspect that what would happen is the VI would break because the reference is not in there, but maybe I am mistaken.

Matt

[nslogan]

It runs but gets the exact same error.

[Donovan_B · Accepted solution]

What version of LabVIEW are you using? In LabVIEW 2011, if controls or indicators on the FPGA front panel had a newline or carriage return in the label, the item would populate in the Read/Write Control node, but you would see this error. It looks like Input Data (Synchronous Display) likely has a newline character that might cause this. That issue was fixed in LabVIEW 2011 SP1, but what happens if you remove the newline and recompile the FPGA VI?

[nslogan]

We're running LabView 2011, not sure on the service pack.

I'll try removing that new line and check back.

[nslogan]

That worked, so I marked your answer as the solution. Thanks!