FPGA Flat Sequence Problem

[VicEngineer]

Hello,

I've been working in Labview RT for the last few months developing a data acquisition project. I recently added in a process for calibrating strain gauges connected to a C series 9237. I'm using two cRio chassis in this project a 9068 and a 9067.

My problem is that I have a flat sequence created in the FPGA code for performing the straing calibration prior to starting the continous data acquisition loop. The calibration is based off of the Example project found in labview 2014 for the 9237 module.

I keep simplifying the FPGA code trying to determine what the system is getting hung up or stuck on, originally I had the sequence setup with a while loop and would terminate the loop after the calbration finished. It seemed to be stuck in the loop so I changed it to a for loop that iterated twice. Same problem the system seemed to get stuck in the loop. In the current version of the code I have it setup as a flat sequence with the acquisition code and IRQ requests duplicated twice. Once for performing the offset calibration, once for the shunt calibration for determining the gauge adjustment factor. 

If you look at the image attached or the code (its a huge Vi sorry) the fpga never makes it to the last frame of the flat sequence where IRQ 6 is set to wait for the RT to acknowledge, the RT system sits and hangs at the Wait On IRQ Method for interrupt 6. The FPGA seems to progress through the sequence and acquire data and somewhere between the last data acquisition and turning the Shunt Cal Enable off the FPGA gets stuck.

Any help or suggestions would greatly be appreciated. 

[VicEngineer]

Update, I've removed some of the local variables I was using for providing me with feedback from the FPGA execution and further linearized the the flat sequence code in the FPGA.

If I run the RT code in "Non-Reentrant execution" with "Highlight Execution" enabled the system propagates through the initialization routine, the IRQ requests are invoked and the system progresses to the Continous Data Acquisition loop.

However if "Highlight" execution is not run the system gets stuck somewhere before "IRQ acknowledge 1" this IRQ is responsible for sending the trigger signal which initiates the start of continous data acquisition.

Any thoughts? I'm going to further simplify the FPGA code into two Sequential Flat sequences but apart from that I'm running out of ideas. As far as I understand I have not created any race conditions in the FPGA code, any advice or suggestions would be greatly appreciated.

[Jacobson-ni]

Vic,

I would try to monitor the Timed Out portion of the Wait on IRQ nodes you have to make sure that you are actually acknowledging every IRQ.  I noticed when you Acknowledge IRQ 5 in your RT code you only wait 1.5 seconds instead of -1.  It is possible that the step does not complete in 1.5 seconds but using highlight execution gives it enough time to complete.

[VicEngineer]

The data acquisition is set to run at 1613 Samples/second I request a finite acquisition of 1613 samples it should only take 1000ms. Could take 2 seconds if it just missed one acquistion loop though.

I am acknowledging every IRQ number, I read another post and a white paper on a similar manner. It was inferred that a thread is consumed for every IRQ signal waiting to be acknowledged, from this I went through and double checked all my Vi's to make sure that the IRQ's are properly acknowledged.

I changed the wait time to -1, that seems to have rectified one of the problems. Thanks for that I don't know why I overlooked something so obvious...tunnel vision I suppose.