Marc,
the emulation mode offers only pass-through access to the I/Os of an R-Series board. As the Xilinx compiler isn't involved, there is no way to get an idea about the number of gates your code is going to use.
In fact there is no easy way to predict the FPGA usage of a program, as the Xilinx tools do optimization runs if required. E. g. if a piece of code uses 50% of the FPGA this doesn't mean that doubling the code will result in a 100% usage as the Xilinx compiler starts optimizing the code size, if it runs out of gates. In a scenario like this, you may even be able to triple the size of the code without running out of gates.
Still there is some help for estimating the FPGA uitilization of LabVIEW code. Please
click here for more information.
Kind regards,
Jochen Klier
National Instruments