LabVIEW
FPGA IO Node behaviour
I am troubleshooting a system remotely so am unable to test this for myself.
How does the FPGA IO Node on a cRIO FPGA work in the situation were you try and read from multiple channels on an AI card (an NI-9205 to be specific) which has a minimum conversion time of 8us.
I would of have expected the code in the image below to take 256us to operate (8us x 32 channels).
This doesn't appear to be the case though, instead it appears that this is not limiting the execution time of my FPGA in any way.
I am wondering if instead the FPGA continuously acquires data from the card at the conversion time in its settings and this node just returns the most recent value. In other words I am wondering if this node is not blocking.
It actually depends on the module you try to access. Modules with Simultaneous Sampling on all channels normally will enforce the configured sampling rate. Others will simply read the last conversion value for each channel.
@rolfk wrote:
It actually depends on the module you try to access. Modules with Simultaneous Sampling on all channels normally will enforce the configured sampling rate. Others will simply read the last conversion value for each channel.
This is something I sometime struggle to determine from the the NI datasheets.
I tend to double check this by setting up a simulated cDAQ chassis in MAX, adding the card and creating a task to see what the max sampling rate is.
For an NI-9205 (Which is what I am using in this actual project) acquiring from all 32 channels the max sampling rate is 7812Hz. This suggests that this card does not do simultaneous sampling as that works out at 4us conversion time on all 32 channels
Based on what you have said that means that this would just return the latest value. Do you know if that is actually documented anywhere? I feel like that behaviour should be in the detailed help for the FPGA IO Node
The 4 us conversion time is documented in the Specification Datasheet. But it means a reduced accuracy of ±8 LSB for multi channel acquisition as documented in that document too. If you want to get ±2 LSB accuracy you need to set it to 8us sampling interval.
As to if a module is simultaneous sampling or not, that is fairly easy to distinguish.
- If it doesn't say so in the product description it isn't simultaneous
- If it is a high channel module (> 8 channels) it isn't simultaneous
- if it costs less than 200 bucks per channel it isn't simultaneous
It is pretty obvious that it isn't simultaneous then.
I have just managed to get some additional debug information on the remote system and can confirm that the FPGA loop is running at 1000Hz when all channels are set to a conversion rate of 8us.
If the FPGA IO Node was blocking that would not be possible as the maximum rate would be ~796Hz (1ms+32x8us)
That ties in with what you have said about non-synchronous AI cards just returning the latest value.
I feel like that should be documented somewhere (I certainly can't find it apart from in the link further up this thread)
