FPGA IP core with verilog

[awang_synovus]

How should I import Verilog code into LabVIEW FPGA? I understand how to import VHDL code by using IP integration node or CLIP, and I am just wondering if there is any possible method to import Verilog code.

Thanks in advance!

[David-A · Accepted solution]

You can import verilog into labview by generating a netlist from the verilog which will give you an ngc or edif file depending on whether you are using ISE or Vivado respectively.

From there you can try directly importing the netlist into labview using an IP integration node or you can wrap it in VHDL and create a CLIP from it. I would recommend the later, but you're welcome to try either.

To generate the netlist you'll need your own copy of the Xilinx development tools. Xilinx provides documentation on how to generate netlists using their tools.

[awang_synovus]

Thank you for replying David!

Unfortunately, I dont have Xilinx ISE and I just want to use an IP core from opencores for once, so I dont want to purchase a full license just for this IP core. Is there any othere way to convert the verilog file to netlist?

[David-A]

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 Is there any othere way to convert the verilog file to netlist?

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Not that I know of. 

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Unfortunately, I dont have Xilinx ISE and I just want to use an IP core from opencores for once, so I dont want to purchase a full license just for this IP core.

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You may be able to download an evaluation copy of ISE or Vivado. Not sure if they allow you to export any synthesis files from an evaluation copy though. You would want to contact Xilinx about that.

[Dragis · Accepted solution]

You can download a free version of Xilinx ISE which should be sufficient to generate a netlist. 

http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html

Also, Xilinx supports mixed-mode compilation so you can instantiate a Verilog core from a VHDL component and instantiate the VHDL component in an IPIN or CLIP. This worked several years ago, but I haven't tried it in a while so it's possible it doesn't work anymore.

[awang_synovus]

Thanks Dragis for the link! However, when I go into this link, I can not find the download link for the Xilinx ISE webpack. Could you please help me with that?

[Dragis]

Hmmm... I'm not sure. When I click on that link there is a heading a few paragraphs down that says "Download Webpack Now!" that takes you to the download center. If you can't see that then you might just have to start from the Xilinx homepage and search around a little.

[enkeyang]

I would like to ask what to do if the imported IP core itself violates the timing rules.