LabVIEW
FPGA IP integration node wizard freezes with *.edf import
Hello everyone. I am using LabVIEW 2015 SP1 32bit f 10 Patch, LabVIEW FPGA 2015 SP1 and Xilinx Vivado 2014.4 f2 (windows 7 64 bit)
My task is to integrate the IP block using the IP integration node. IP block format: *.edf (in attachments). This is a CAN bus handler.
This is where the process stops!
Log:
Generating simulation model for this IP...
****** Vivado v2014.4_AR66772_AR65813_AR64601_AR63880_AR63479_AR62969_(AR63524_AR64594) (64-bit)
**** SW Build (by xbuild) on Tue May 19 17:22:27 MDT 2015
**** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
source {C:\\NIFPGA\\iptemp\\ipin2B59EC07395249B6BD3D17134315A5E5\\Vivado\\init.tcl}
# read_edif {C:\NIFPGA\iptemp\ipin2B59EC07395249B6BD3D17134315A5E5\Vivado\CAN_IP_DLW30.edf}
# set_property PART xc7k410tfbg900-2 [current_project]
# link_design -name MyDesign -top [find_top]
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
Design is defaulting to project part: xc7k410tfbg900-2
Parsing EDIF File [./CAN_IP_DLW30.edf]
Finished Parsing EDIF File [./CAN_IP_DLW30.edf]
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2014.4_AR65813_AR64601_AR63880_AR63479_AR62969_(AR63524_AR64594)
Loading clock regions from C:/NIFPGA/programs/Vivado2014_4/data\parts/xilinx/kintex7/kintex7/xc7k410t/ClockRegion.xml
Loading clock buffers from C:/NIFPGA/programs/Vivado2014_4/data\parts/xilinx/kintex7/kintex7/xc7k410t/ClockBuffers.xml
Loading clock placement rules from C:/NIFPGA/programs/Vivado2014_4/data/parts/xilinx/kintex7/ClockPlacerRules.xml
Loading package pin functions from C:/NIFPGA/programs/Vivado2014_4/data\parts/xilinx/kintex7/PinFunctions.xml...
Loading package from C:/NIFPGA/programs/Vivado2014_4/data\parts/xilinx/kintex7/kintex7/xc7k410t/fbg900/Package.xml
Loading io standards from C:/NIFPGA/programs/Vivado2014_4/data\./parts/xilinx/kintex7/IOStandards.xml
Loading device configuration modes from C:/NIFPGA/programs/Vivado2014_4/data\parts/xilinx/kintex7/ConfigModes.xml
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-140] Inserted 108 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 106 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 524.797 ; gain = 338.984
# write_vhdl -mode funcsim {C:\NIFPGA\iptemp\ipin2B59EC07395249B6BD3D17134315A5E5\Vivado\CAN_IP_DLW30.vhd}
INFO: [Common 17-206] Exiting Vivado at Sun Dec 24 23:11:53 2023...
I have another computer: windows 10, LabVIEW 2021 SP1 32 bit. This IP block compiles normally there:
Log in attach.
I conclude that everything is fine with the IP block code, the problem is in the vivado configuration or something. Who has any ideas why the code is not being generated?
