FPGA Module Xilinx Update to 13.4 Won't Compile

[otheredward]

Hello, I recently bought a new computer and have upgraded to LV 2012 with Xilinx 13.4 compile tools. I'm using 32 bit LabView on a 64 bit Windows 7 machine. I have the 7852R FPGA card. I upgraded from LV2011 and 32 bit Windows XP.

When I initially installed everything and tried to compile my FPGA code the compilation failed after 5 minutes and gave me a Xilinx tools error. This happened 3 or 4 times. I reinstalled the Xilinx 13.4 software and it happened again, once, but hasn't since. This could be totally unrelated to my question.

When I try and compile a program that compiled without any problems on my old computer I get a timing violation and the compilation fails. I'm trying to run a 95MHz SCTL but it says the maximum speed for this loop is 93.5MHz. I realized the compilation is nondeterministic so if you have a loop that's close to the limit you should try and compile a few times and it might work. I've tried 7 or 8 times and get the timing violation each time. I never had this problem with the older version of LabView and the FPGA module so I know the hardware is capable of running this loop at this speed. How can I get the compiler to be smarter about this or somehow make this thing compile? I'm sure there are tons of questions like this all the time; feel free to point me to existing threads.

Thanks,

Ed

[Jeff.St]

Hi Ed,

I'm sorry to hear you're having these problems.  Unfortunately I can't seem to find any other documentation about this issue.  Perhaps we could just make your code a little more efficient.  Would it be possible for you to post the VI with the SCTL?  Or maybe a screen shot of the loop?

Best,

[otheredward]

Hi Jeff,

Thanks for the reply and offer to help. Its not so critical that my loop runs at exactly 95MHz. With this in mind, and as no one else has posted anything, I changed the FPGA derived clock to 92MHz, which should be slower than the reported maximum speed, and set the loop to use this slower clock. Then I tried to compile the program.

Now, rather than a timing error, I get a "The compilation failed due to a xilinx error." error. I have no idea how to fix this. I'm attaching the compilation summary and Xilinx log to this post. I would be happy for any help.

The compilation hangs at the "generating cores" stage for about 6 minutes and then fails. No idea what the problem is.

Thanks,

Ed

[T-REX$]

Hello Edward,

According to the Xilinx log, you're running into an error because one of the Xilinx components doesn't have permision to edit the file located at 


   "C:\NIFPGA\jobs\MFfjl6n_XI64xG6\core_BuiltinFIFOCoreFPGAwFIFOn2\tmp\_cg\_dbg\

   ReallyLongUniqueName_ReallyLongUniqueName_xsd\fifo_generator_v8_2\xil_6076_61"

There are a couple things that could cause the error. I suspect that your firewall is blocking the 13.4 tools, as mentioned in Xilinx AR #33766.

[jspinozzi]

I had a similar set of problems which happened to me on 3 very different but new computers all freshly installed with the 2012 DS2 developer's suite, primarily focused on LabVIEW 2012 and Xilinx 13.4 for a recent project.  Compile gave numerous Xilinx compile errors, also claiming it didn't have access or permission to a file. But depending on the file I chose to compile, or how I changed the diagram or disabled parts of the diagram (similar to how the previous poster changed his timing to 92MHz) I would get another error of a different type, but never on all three computers could compile using 2012 & 13.4.  Instead took same code to two other computers running 2012 and Xilinx 12, and they compiled fine.  Removing and reinstalling entire DevSuite didn't help, and then downloading specific installers for LV2012 and Xilinx13.4 also didn't solve the problem (along with minimum requirements for NI FPGA, NI RIO, and Device drivers of course).  No luck on any LV2012 computers, but never a problem on LV2011.  Also tried simplistic FPGA code (like a boolean control wired to a boolean indicator, inside a loop) and that wouldn't compile either.  

I don't think Xilinx AR 33766 helps, I am 100% sure there is no antivirus on any of my three computers, and the errors I get are different than the one shown.

I also wondered/suspected that this might be a x86 vs x64 thing? 

Problem not solved to date, and I probably won't have the time to try to solve it.  Will just carry on compiling LV2011 until I hear this has been solved?

Below are some of the many errors I got, in hopes people will be able to search/find these in the future: 

WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
for the specified device family.

ERROR:Xst:1850 - Unable to insert IOBUF on port <dio40> in unit <window> having KEEP_HIERARCHY constraint. There are feedbacks in other units.

ERROR:sim:928 - Could not open destination 'PkgCartridge.vhd' for writing.

ERROR:sim:928 - Could not open destination 'PkgBeatleTypedefs.vhd' for writing.

ERROR:coreutil - ios failure

WARNING: [Netlist-8] Can not read encrypted file 'C:\NIFPGA\jobs\Ov016Yx_B0lT1MQ\CcHsOutputLogic.vhd' because xlicmgr command failed; please check the xlicmgr messages at the terminalParsing VHDL file "C:\NIFPGA\jobs\Ov016Yx_B0lT1MQ\CcHsOutputLogic.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

[jspinozzi]

Oh, also 

1) Tried to check permissions on the c:\NIFPGA folders and the folder(s) where I suspected it was writing intermediate or .vhd files.  No luck but I wasn't exhaustive about this

2) Licensing issue is mentioned in one of the errors.  Could it be a licensing thing?

3)  One PC was Win8 and other two were Win7.  All three were x64

That's all the clues I have for now. 

[LVAC]

I am also using Xilinx 13.4 because I have labview 2012 SP1 and have tried many time to compile the example for 9222 a simple example, But I can not compile the code.

I download the Xilinx 13.4 which takes many minutes(hour)4G file.

I use local compiler

I get a message saying X10.1 can not compile   but I am using a new version X13.4 

Do i have to downgrade to X10.1 ?

[LVAC]

more info

Project: NI 9222 Getting Started.lvproj Target: FPGA Target (RIO0, cRIO-9101) Build Specification: MyFPGACode Top level VI: MyFPGACode.vi

Compiling on local compile server Compilation Tool: Xilinx 10.1

Compilation Submitted: 5/30/2013 6:40 PM

Run when loaded to Fpga: FALSE

Xilinx Options --------------------------------------- Design Strategy: Timing Performance Synthesis Optimization Goal: Speed Synthesis Optimization Effort: High Map Overall Effort Level: Default Xilinx setting Place and Route Overall Effort Level: High

JobId: Working Directory: C:\NIFPGA\compilation\NI9222GettingSta_FPGATarget_MyFPGACode_a2IcXYkvUxI

LabVIEW FPGA:  The compilation cannot be performed by the compile worker. The compile worker may be configured incorrectly for this compilation, or it may be in an error state.

[LVAC]

tried to load x10.1 because maybe the virtex-II of cRIO-9024 needs it to compile but hit a road block

LabVIEW FPGA Module Xilinx Tools 10.1

It provide no download like X13.4

to many roadblocks

[LVAC]

Working.

Example i was using needed to replace the chassis with my customers chassis (9114) in the project file.

X13.4 complied

used FPGA LED of Chassis   to validate it was controlling the fpga hardware after compile and download

Remember the compiler in my case had to be download then you will see it under

Under MS Start button - National Instrument(r) - FPGA - FPGA compiler worker (after X13.4 Xilinx compiler download)

(NI-9222 Analog input were not setup in this example - only assigned in project)