Sketchy details to start -- I cannot post the source code to the forum.
Dell PC, Windows 7-64, LabVIEW 2012, LV FPGA 2012, PCIe Bus to PXI Chassis with
NI PXI-7951A with NI 6581 Adapter Module
FPGA uses DMA FIFO for fast data transfer from Windows to FPGA in PXI Chassis.
A data array is created by a Windows process, then written to a Shared Variable (SV).
Next the SV contents are written to the DMA FIFO, again by a Windows LV module.
The FPGA process reads the DMA FIFO one element at a time, then interacts
with hardware on digital I/O lines, using the data.
The setup works fine for about 60 seconds, then crashes without any reported error.
In 60 seconds, I can run the process over 20 twenty times, or 8 times, or once, or not even once.
Either way, after 60 seconds passes, it acts like the FIFO just stops working. It can
be in the middle of a run, when the FIFO is still partially full, or it can be
between runs, but when 60s is up, the FPGA process seems to hang up.
The only thing I see that looks like a clue is the Tools\Options\Shared Variable Engine\Sleep Time field,
which defaults to 60 seconds. I've tried to change this number, but I cannot change the behavior.
If, in a Windows loop, before 60s elapses after I open a reference to the FPGA, I close the FPGA Reference,
then re-open it, everything works fine.
Grateful for any ideas or links to NI manuals that could shed light on:
> Shared Vars
> DMA FIFO
> Reference Engine
Many thanks. I realize it's very difficult to help without the source code.
BTW, I've used this hardware configuration successfully in other projects. This project lead me to use
the SV and DMA technologies for the first time.
Funk
