FPGA Sampling Rate Issue w/ 9205 Module

[mjochinsen]

I would suggest:

- match the data type (FXP and I16). You are passing a Fixed point to a DMA set as integer. This might be why you are getting zeros.

- check if there are elements to read on the host with the property node. If # of elements to read is < # you want to read then do something else (or nothing )

- check if you are timing out the FIFO (target). Use timeout different from 0 (0 never times out, -1 waits forever). If you are timing out you are probably wrtiting too fast, reading too slow or FIFO is too small

- use shift registers to pass the error (host)

- set the sample rate (host) before you start reading the FIFO