FPGA Timekeeper syncing to RT (1588) reference time

[akarpilow]

I have a cRIO 9068 that is synchronized to absolute time using 1588 (the NI-sync library).  The cRIO also has an NI 9215 module.

My objective is to trigger sampling and reporting of samples in the FPGA (and timestamp) as precisely as possible. To do this, I tried using the Timekeeper library and the RT reference time (conditioned by the 1588 grandmaster).

These are my steps (see attached figures):

1. (RT): using NI-sync, sync the RT clock to the 1588 distributed UTC time - this appears to be working (status is synchronized and reference time is accurate)

2. (RT): send the niSync Get Time to the FPGA (updating every 200 ms). 

3. (FPGA): latch the timekeeper to RT using the updates (from the timekeeper examples) - this partially works (the timekeeper "get time" yields a reasonable time but the timekeeper never locks)

4. (FPGA): create a metronome/clock based on the timekeeper time. 

The problems I've observed are that the "FPGA Timekeeper locked" keeps alternating (T/F). When it's false, the reported "offset from RT time (ns)" is fixed at 0. When I compare  the RT time and the FPGA timekeeper time on the FPGA (in the loop labeled "Synchonize to RT time"), the errors range up to 2 ms.  Finally, in the metronome loop (labeled "subPPS Signal Generation"), I observe that the time snapped event occurs regularly - indicating a discontinuity in the time reference.

I realize that this configuration cannot yield very high accuracy time reference given the accuracy of 1588 (~ms) and the nondeterministic delay between the RT and FPGA communication.

1. Is this the best configuration I can achieve given the equipment (only crio 9068s) and the time dissemination method (1588)? 

2. Why does the FPGA timekeeper never lock to the RT time?

3. Does the frequent "time snapped event" in the metronome loop mean that this clock/metronome is not reliable?

Thank you for any advice you might have!

Best,

Alex

[akarpilow]

Really hoping for any sort of advice as to how to better sync the FPGA timekeeper to the 1588 time (RT). 

1. Using the code provided in the timekeeper examples, it looks like the FPGA timekeeper should be able to sync to the system time (also it was suggested here: https://forums.ni.com/t5/Real-Time-Measurement-and/1588-synchronization-of-distributed-cRIO-systems/...). But the boolean "FPGA timekeeper locked" is regularly going false or never goes true.

2. Furthermore, I thought 1588 Software synchronization would sync the system RT clock (as suggested here https://www.ni.com/en/shop/compactrio/choosing-a-compactrio-synchronization-technology.html). However, on the RT processor, when I compare the system time (via Get Date/Time in Seconds) to the NI-Sync Get Time, it's usually off by around a ms. Which clock time should I send to the FPGA timekeeper (NI Sync or system Get Date/Time)? 

3. Finally, with the FPGA timekeeper, I'm creating a metronome for reporting data. If I measure the ticks between the rising edge of the metronome, it appears that when the timekeeper gets an update from the RT clock, there's a huge spike in this period (+/- 10 ms). I understand the latency between the RT processor and the FPGA is nondeterministic, but is there anyway to smooth/reduce these spikes? Should I just increase the time between updating the FPGA timekeeper (although then the clocks might drift even more)?