FPGA Timing Error

[InfiniteNothing]

I'm getting this error when I try to compile. Any insights?

Clock Rates: (Requested rates are adjusted for jitter and accuracy) 
  Base clock: 40 MHz Onboard Clock
      Requested Rate:      43.230157MHz 
      Theoretical Maximum: 46.474880MHz
  Base clock: MiteClk (Used by non-diagram components)
      Requested Rate:      33.037101MHz 
      Theoretical Maximum: 66.233938MHz
================================================================================
Timing constraint: TIMEGRP "cRio9205_dio38" OFFSET = IN 16 ns VALID 16 ns 
BEFORE COMP "dio36"         LOW;

 1 item analyzed, 1 timing error detected. (0 setup errors, 1 hold error)
 Minimum allowable offset is   2.536ns.

Hardware: sbrio 9642

Labview 8.6.1

NIRIO: 3.2

Message Edited by InfiniteNothing on 04-19-2010 03:10 PM

[muks]

See here

[muks]

And also check this discussion

[InfiniteNothing]

I tried the solution from the first link though and it didn't seem to work. I wonder why NI doesn't give a bit more information on exactly what that patch fixes. 

As for the second link, I'm not using FIFOs or SCTLs at all. I just had an analog input, some math, and an analog output.

I did end up fixing the problem: I moved the analog output to the same node as the analog input using a shift register to carry the data that was destined for the output. I'm not sure why that fixed things and I had that code compiling just fine before some tweaks to the math. I was just hoping to figure out what not to do so I don't hit that problem again. It's frustrating when it takes so long to compile only to throw that error.

[muks]

Glad you fixed it and thanks for sharing the info...