FPGA VI modified after each opening

[Vladimir_Drzik]

Hi guys

I've got an annoying problem with FPGA module. In a specific situation, my FPGA VI is modified each time I open it. That means I always have to recompile it, which takes quite a lot of time. Moreover, in another specific situation, the project containing the FPGA target is modified each time I open the FPGA VI. Which is not so annoying, but still...
Let me demonstrate both of the problems on the attached project. When you open Always Modified.vi, the VI gets modified, and so does the project. After some research, I realized that the VI modification is caused by the VI-scoped memory configuration. Also, it looks like some VI-scoped FIFOs are causing it, too.
Why is this happening?

Vladimir

[BillMe]

I don't have IMAQIO support so I created a new FPGA target using the 7831R and put your VI under that...after opening your Always Modified.vi and saving it, I can now open it and close it without it asking to "Save". So I couldn't recreate your problem.

Message Edited by Bill@NGC on 07-17-2007 09:12 PM

[Vladimir_Drzik]

Hi Bill

Can you try to install IMAQIO support? It is not necessary to have a card installed to open my project. I have already reproduced it on two totally different machines so it does not seem like a random problem.

Vladimir

[mrak1]

Hi,

You may need to do a mass compile on the LabVIEW Directory after installing your driver.  I know that some things on a typical LV FPGA block diagram ( such as the IO nodes or the single cycle timed loop) actually have subVIs of their own that you cannot see.  Therefore, if there are changes to these system VIs from installing the driver, then you will have the * on the VI each time you open it. 

Warning ==> mass compiling the LabVIEW directory could take several hours ==> it is best to do overnight!

I hope that this helps,

Mike

[Vladimir_Drzik]

Hi Mike

Thanks for your help, it seems like the mass compilation helped with the modification of the VI itself. However, it did not help with the modification of the project. Do you have any more ideas?

Vladimir

[mrak1]

Hi,

Here are a few questions:

• When the project is requiring you to save ==> is it also forcing you to recompile the FPGA VI after you save the project? 
• Are any of the files in the project marked as read only ( such as the alias file or other VIs)? 
• If you click close on the project without saving, it should give you a list of what VIs?  Are any of these VIs actually not saved?  Are there any VIs on the list?
• If possible, try creating a new project with the same VIs and bitfile and see if you are still having the same problem.

Good luck and let me know,

Mike

[Vladimir_Drzik]

• hen the project is requiring you to save ==> is it also forcing you to recompile the FPGA VI after you save the project?
  

No it's not

• Are any of the files in the project marked as read only ( such as the alias file or other VIs)?
  

No there aren't any

• If you click close on the project without saving, it should give you a list of what VIs?  Are any of these VIs actually not saved?  Are there any VIs on the list?

Only the project file itself is listed

• If possible, try creating a new project with the same VIs and bitfile and see if you are still having the same problem.

It makes the same problem. Actually, this is quite well reproducible.
If you compare the project files on disk before and after the "modification", you see that nothing has really changed.

Vladimir

[Oli_Wachno]

Hi Vladimir,

this sounds a bit familiar to me. When I was still using LV7.1.1 / FPGA 1.1, the FPGA module  insisted on recompiling the bitstream  every time I opened the project. The bitstream manager always showed that the bitstream needed recompiling.... I tried alomost everthing and finally ended up uninstalling all NI software and reinstalling.... from that moment on everything worked fine again.

Which version are you using?

Cheers

Oli

[Vladimir_Drzik]

Hi Oli

Thanks for your suggestions. I'm using LV 8.2.1 with FPGA module 8.2.1. Actually, since I did the mass compile, it no longer wants to recompile the bitstream each time I open the VI. So it's not that annoying now. It just modifies the project file each time I open the VI. The main annoying thing about that is that we are developing under source control, so the project file is usually read-only for me and cannot be saved.

I've already tried to reinstall NI software, though for a different reason . The issue persists, and it does so on multiple different machines.

Vladimir

[Yi Y]

Hi Vladimir,

I tried to open up your attached project and I wasn't able to reproduce the problem.  The project file does not change on open.  I have LabVIEW 8.2.1 and FPGA 8.2.1 as well.  Have you tried to open up the files you included in the ZIP file and see if it's reproducible on all your machines?  Is it possible that your project is loading up other files that are modified?  When you list unsaved changes, what files are listed? It's most likely happening because of your installation of LabVIEW, but it's difficult to pin point this issue without it being reproducible.

Yi Y.
Applications Engineer
National Instruments
http://www.ni.com/support