FPGA adding delays between siganls

[Eletrostatic]

Hi,

Could some one give me a good example of adding delays in a FPGA using a state machine SCTL. I want to add some ns delays between a CS and CLK. Tried using a tick counter to trigger the next state but did not work.

Thanks

[Omar_II]

You can not put any delays in a SCTL. That would defeat the SCTL.

You will have to have some kind of a state machine with a state for the CS and another state for the CLK and a state to count the number of clock cycles needed between the two.

How where you counting the clocks ticks?

[Spectre_Dave]

Use a flat sequence to in a normal while loop.  I have attached a screen shot of a DSM reader.

[Eletrostatic]

So I am trying to add delays between the CS and SCLK of a SPI driver. See here http://zone.ni.com/devzone/cda/tut/p/id/9117

Problem is the driver is in a 40Mhz timing loop. I have added extra states between when the CS goes active and inactive in relation to the SCLK but having problems finding a way to waste some time in that state. Adding one extra state before should take 1 clock cycle right? But it seems to have little effect.

[Eletrostatic]

Was thinking of something like this....Not sure it would work, have to try on the HW tommorrow. Basically add the state inbetween the signal changes. Count the ticks and select the next state based on that!?