FPGA: compilation error: size of concat operation is different than size of the target

[Harlequinade]

Today I got an error, for which I couldn't find a solution.

I use the PXI-7813R FPGA, with Xilinx tools 10.1

At compilation, the error I get is:

Compilation failed due to a Xilinx error.

Details:

ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/TESY1S8_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 301. Size of concat operation is different than size of the target.

ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/TESY1S8_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 372. Size of concat operation is different than size of the target.

--> 

Total memory usage is 185944 kilobytes

Number of errors   :    2 (   0 filtered)

Number of warnings :    0 (   0 filtered)

Number of infos    :    0 (   0 filtered)

Process "Synthesis" failed

Start Time: 18:25:26

End Time: 18:28:54

Total Time: 00:03:27

What can cause a concat size difference?

[Harlequinade]

I deleted some non-trivial FIFO related stuff and suddenly worked again. Although I ain't sure if that was the reason.

[Harlequinade]

No, it appeared that wasn't the reason. After some minor modifications, a recompile was necessary.

First, I got an unexplained error. No error code. That the vi was not in a state for compilation, (have seen this before and is then often marked as error code 1000).

Second, I opened all my subVIs and made minor movement on a single indicator to force recompiling of the subVIs.

Third, at rebuilding, the same error occured:

Compilation failed due to a Xilinx error.

Details:

ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/IBj6Ib7_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 301. Size of concat operation is different than size of the target.

ERROR:HDLParsers:804 - "C:/NIFPGA/jobs/IBj6Ib7_X4PR8hn/NiFpgaAG_000000ce_CaseStructureFrame_0000.vhd" Line 372. Size of concat operation is different than size of the target.

--> 

Total memory usage is 185688 kilobytes

Number of errors   :    2 (   0 filtered)

Number of warnings :    0 (   0 filtered)

Number of infos    :    0 (   0 filtered)

Process "Synthesis" failed

Start Time: 17:36:10

End Time: 17:39:38

Total Time: 00:03:28

Any suggestions on solving this error?

[Harlequinade]

This is by the way the configuration:

Project: FPGAWrapperMG100125AOD.lvproj

Target: FPGA Target (RIO0, PXI-7813R)

Build Specification: fpga_integrator_AOD_random_access

Top level VI: fpga_integrator_AOD_random_access.vi

Compiling on LabVIEW FPGA Compile Cloud Service

Compilation Tool: Xilinx 10.1

Start Time: 05.07.2011 19:06:12

Run when loaded to Fpga: FALSE

Xilinx Options

---------------------------------------

Design Strategy: Custom

Synthesis Optimization Goal: Area

Synthesis Optimization Effort: Normal

Map Overall Effort Level: Default Xilinx setting

Place and Route Overall Effort Level: High

JobId: FNW72uPWorking Directory: C:\NIFPGA\compilation\FPGAWrapperMG100_FPGATarget_fpgaintegratorAO_9D5B4237

The Xilinx log is attached.

[jtagg]

HI Harlequinade,

it seems that the problem could come from a case structure from the message. However it may not be a problem with the case structure but its content.

Could you post your FPGA VI so I can take a look at that?

Regards,

Joseph Tagg

[Harlequinade]

The project is a bit large and complex. Is it okay if I can send it to you personally?

[jtagg]

Hi,

have you tried as I suggested with a local compile server?

Does that help?

Regards,

Joseph

[Harlequinade]

Local and remote compile server doesn't seem to make a difference.

When things don't compile here, we use the magic trick to force recompile, which is the following work-around.

i) open all subVIs & controls

ii) move a control on FP or BD by a pixel and save each file

iii) try to compile again

[Dragis]

You can also force a recompile by holding Ctrl and clicking the Run arrow. Doing so will force a compile but will not start running the VI when the compile is complete.

[Harlequinade]

True, but it somehow doesn't force the FPGA compiler to see the subVIs as changed. 

I tried it, but it didn't help me. Changing all VIs and clusters saved in controls did the trick for me. I'm just writing it down, such if someone has the same problem, he/she could try this out.