FPGA compilation ignores selected Clock Source

[Aditya_Dhananjay]

Hello All,

I am trying to compile an FPGA VI using a 60MHz derived clock. I've attached a screenshot of the relevant code in the top-level VI. 

The FPGA compilation succeeds (in a manner of speaking), but the compilation log shows that the VI has been compiled at only 40MHz (as opposed to the expected 60MHz). Again, I've attached the relevant screenshots.

My setup:

LabView 2014 (32 bit)

LabView FPGA 14

Vivado 2013.4

Development machine: Windows 7 Professional with 32GB RAM

I attempted the compilation on the local compile worker, as well as on a remote Linux-based compile worker, and the results are the same.

I attempted to restart the computer and try again. Same results.

Any help would be greatly appreciated!

Best regards,

Aditya

[Aditya_Dhananjay]

I should have mentioned: The target device is the NI 7976R FPGA board.

[Riv]

Any chances that in the project window you changed the clock's name only but not the frequency? (simple mistake but can happen)

Does the problem occure in other projects for this target, too?

I have LV 2014 at work so I will try to dig a bit deeper tomorrow.

[Aditya_Dhananjay]

Hello Rivulet,

Thank you for your reply.

I verified that the 60MHz is indeed correctly chosen. Here is a screenshot for your reference.

Thanks again.

Best,

Aditya

[Aditya_Dhananjay]

And to further clarify: If I were to compile against an 80MHz (2:1 Derived) clock, it works. As in, the compilation fails due to a timing violation, but at least it attempts to compile the FPGA to run at 80MHz. Similar with 120MHz.

The weird behavior is just with 60MHz (as far as I have tested).

Thanks again.

best,

aditya

[Aditya_Dhananjay]

Update: I deleted the 60MHz clock, created it again, and then selected it as the timing source in the top level VI. Recompiled it. The problem remains. The compiler still compiles it at only 40MHz.

[David-A]

Can you post your code? I just tried compiling a SCTL that uses a 60MHz clock derived from a 40MHz clock on my 7976 and it worked fine.

[Aditya_Dhananjay]

Hello David,

Thank you very much for your time and help!

a. When I try to compile a simple VI, the compilation works at 60MHz.

b. When I try to compile something more complicated (download link below), the compilation just uses the 40MHz clock.

http://www.cs.nyu.edu/~aditya/Large_Project.rar

In the project navigator, please navigate to "RT PXI Target" -> "FPGA Target" -> "Streaming_Vulcan.vi". This is the top-level VI that I'm trying to compile at 60MHz. 

Thank you once again for your time. I really appreciate it. 🙂

Best,

Aditya

[David-A]

I was able to successfully compile your FPGA VI with the 60 MHz clock source. See attached image.

My guess is the issue has something to do with the compile worker. Maybe try repairing the compile tools on the computer you are compiling on.

Also, are you seeing odd behavior from the compiled bitfile? Maybe it is just the reporting that is not working and the actual compile went exactly as expected. 

[Aditya_Dhananjay]

Hello David,

I greatly appreciate the time you've put into helping me out. Thanks for performing the compilation on your system. I'm glad to know that it compiles successfully on at least one machine. 🙂

I will repair the installations and try again. Thanks for the suggestion.

We do not yet have the 7976R FPGA board, so it will take some time before we can test out the bitfile. In the meantime, I'll try the repair installation option, and attempt the compilation again.

Best,

Aditya