FPGA compilation ignores selected Clock Source

[Aditya_Dhananjay]

Hello Newton,

Thank you for your message. You can download the code here (I reactivated the link):

http://www.cs.nyu.edu/~aditya/Large_Project.rar

(In the project navigator, please navigate to "RT PXI Target" -> "FPGA Target" -> "Streaming_Vulcan.vi". This is the top-level VI that I'm trying to compile at 60MHz. )

Thanks again for your time!

Best,

Aditya

[hnesmith]

A Corrective Action Report (CAR 473968) was found which documents the issue we are seeing. This CAR was recently filed so it just missed the 2014 release. The issue is isolated to the compile report and the timing of the clock is correctly configured in the compilation.