FPGA compile crashes frequently

[pd2]

Hello,
I have been working on an FPGA project. I am using LabView 8.5 with the FPGA module version 8.5. My target is a PCI-5640R. I am running Windows XP.

When I compile the FPGA, I frequently get errors. I originally was using arrays and clusters in the FPGA, but I got a tip that the compiler might not work well with those; so I migrated to memory blocks, but I am still getting errors.

I will attach a file with some old compile logs with errors that I got when I was using arrays and clusters. I will also attach my current project. The FPGA has a block which performs an FFT on incoming data. I am on my fourth compile attempt now. The first one failed due to circumstances outside of LabVEIWs control, but the other two logs are in the zip with the project.

I really need to get this working soon as I have a deadline approaching quickly.

Thanks


EDIT: I don't know if this helps, but twice in the past, when I started a compile, I just got a message box which said:

xflow.exe - Entry Point Not Found
The procedure entry point ?get_vendor@PM_PIC@@QBEQADXZ could not be located in the dynamic link library libPersonalityModule.dll.

However, this does not happen anymore.

Message Edited by pd2 on 07-15-2008 09:57 PM

[pd2]

The fourth compile completed successfully. This has happened many times before. The compile will fail frequently, but it works occasionally. I'm good for now, but if you know any way to prevent this hassle in the future, let me know.

Also, the compile took about 45 minutes. If there is a way to cut down on compile time, let me know that too.

[JerryAL]

Hi

Your project LV FPGA VI compiled for me the first time.

I’ve attached the statistics for the build report.

As for why it may not be compiling all the time, or sort of randomly, I’m wondering if it may be the timing. 

  Base clock: ADC_0_Port_A_Clk
      Requested Rate:      25.001250MHz
      Theoretical Maximum: 25.661423MHz

The theoretical maximum is just a tad bit faster than the requested rate.  I’m wondering if on the other compiles, that the compiler couldn’t come up with a logic layout that met the 25 MHz.

Is there any more pipelining you can do to your processing VI to get the margin up a lot higher.  I saw in your processing case that there is a long chain of logic which may be pushing the theoretical time down to close to the requested time.

The other thing to try to verify this is to change the ADC clock Requested Rate down to 12.5 MHz, and see if it compiles easier.

It also might be a good idea to place your processing logic in another SCTL, passed through another FIFO.  Run this off the RTSI Clock.

Jerry

[pd2]

I like the idea of running the processing on another SCTL because then I could use a faster clock to get things done quicker. I am sure I would have to add more pipelining to do so.

Thanks for the advice.