My FPGA VI compiles without error. If I add Single-Cycle Timed Loops (SCTLs) to it and try to compile, LabVIEW crashes while generating intermediate files, at step 4 of 6.
I'm running LabVIEW 8.5.0 under Windows XP on a Dell M6300 with an Intel Centrino Duo.
After experimenting a bit, I created a minimal VI that replicates the problem.
The VI is simply an SCTL containing a case structure. Each case writes to the same boolean global variable, and my guess is that this is the problem.
Am I not allowed to write to the same global more than once in an SCTL, even if a case structure guarantees that only one write would actually occur?
The enclosed VI demonstrates this, although I didn't enclose the globals file, so just create one and link the two globals in the case structure to the same boolean global.
Thanks.