FPGA: control inside a condition don't pass data

[Pierre_F]

Hi! I would like to  to share with you a strange behaviour I've just had in FPGA /labview 2020

Inside the FPGA code, I wired the timeout output of a DMA FIFO "read" to a condition containing  several logic  functions + inputs updates, that are supposed to execute when the FIFO triggers an event.

Strangely, some code inside the conditions don't execute. look below:

Those inputs works correctly when they are placed out of this condition structure.

I've tried with standard controls, local variables, selectors (below) but the problem is persistent.

regarding LabVIEW paradigm, it's completely illogical.

It behaves as if the compiler doesn't understand the situation, and decides not to pass any value.

can someone explain this? 😥

[natasftw]

Why would you not the output of timeout? when it's only being used with the case structure?  You can just swap the cases.

That said, your post contradicts itself and doesn't include a lot to look at for us to help you.  You say it works if you remove it from the conditional structure (case structure).  But, your picture below has it circled in red saying it isn't working with selectors.

It seems likely you mean if you remove the bits from the while loop.  If you're not able to post what you're working with, can you at least post a screenshot of what DOES work?  That will help us determine what's different to help you debug that.