FPGA custom trigger for PCIe 5763

[JayLizd]

Thank you for all the insight. I will try to modify the streaming api and see what I can get done. I will also look into getting a state machine into the FPGA code! 

[JayLizd]

For anyone wondering... I edited the Data Stream Control vi (FPGA) . I edit the stream it enters after finishing a finite transfer. After a finite transfer is finished the stream state goes into a "Done" state which then switches the case structure diagram into "Done". Inside the "Done" case structure there a sub case structure with inputs being "Idle" and " Finite Transfer and Continuous" Inside the "Finite Transfer .... " case structure  the stream state stays in "Done " state so I switched the "Done" state to "Idle" so it restarts the Finite transfer through the FPGA. On the host side I added logic to compensate for this.

[Terry_ALE]

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@JayLizd wrote:

For anyone wondering... I edited the Data Stream Control vi (FPGA) . I edit the stream it enters after finishing a finite transfer. After a finite transfer is finished the stream state goes into a "Done" state which then switches the case structure diagram into "Done". Inside the "Done" case structure there a sub case structure with inputs being "Idle" and " Finite Transfer and Continuous" Inside the "Finite Transfer .... " case structure  the stream state stays in "Done " state so I switched the "Done" state to "Idle" so it restarts the Finite transfer through the FPGA. On the host side I added logic to compensate for this.

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Good to hear.

Since this is a common LabVIEW FPGA library, I assume this gets copied and pulled into the project specific code.

If possible, it may be good to look into contributing this to the NI LabVIEW FPGA github repo: https://github.com/ni/labview-fpga-examples