FPGA delay using derived clock

[Andrew_Quick]

Hi,

Probably a simple answer to this. I have the PXI-7813R which has a base clock of 40 MHz. I need to create a time delay of 488nSecs in my code. Unfortunately with 40MHz I have to either choose 475nSecs or 500nSecs. If I use a derived clock of 80MHz I can get a delay of 487.5 which is very close to what I need. However, if I change my top level clock to 80MHz I get various timing violations during the compile. Is there a way to keep the top level clock at 40MHz but use the 80MHz clock for a time delay?

Thanks

Andy

[Sil.VI · Accepted solution]

Hi Andrew_Quick

Are you using that derived clock on a SCTL? I have done some research on your issue and found the following Knowledge Base article that talks a little of the way that derived clocks work with the SCTLs and in the botttom section there is a note that some code may not compile at rates above 40Mhz because of the timing constraints of the FPGA, so I think that you should check that you did not get any warnings or suggestions at the moment of creating your derived clock for your target.

Even if you select the 40 MHz clock as the top level, if you select the 80 MHz clock for the timed loop the compiler will have to make all the functions fit in the FPGA and depending on the error you get that could be what is causing you the timing violation.

Hope that you could find this helpful !

[Andrew_Quick]

Hi,

Thank you for the reply. I am fairly new to this and did not realize that an SCTL could take a different clock than the top level clock. Anyway, I found my timing violation and fixed it so I have been sucessfully compiling the whole VI with a top level clock of 80MHz. If I run into an unsolvable timing violation later as I add more code then I will use the SCTL idea.

Thank you.

Regards

Andy