FPGA - host and target timing

[Chupka993]

Hello Nathand.

Thank you for your help. I need the entire history of data, so I can't replace graph with chart. I've made changes that you've suggested to me. Now I have another problem with communication between Host and Target. When I remove delay from Host VI, signals from Host come extremly late to the Target and I don't know why. 

Can I avoid shift register in combination with growing arrays? How can I save all my data and avoid problem with constantly-growing memory use? Can I somehow add new elements to the end of the array without using shift register? 

Thanks in advance

[charansai]

Hey,

One thought on the second part of the question. If you have some estimate of the total amount of data that you are going to collect, you can initialize an array of the estiimated size and replace for each iteration one element this way you can avoid shift registers.

I don't think this will address the memory issue but this is one idea to avoid shift registers .You cannot go on saving the data endlessly you will be out of memory at some point.