FPGA program won't compile any more

[Dave_Thomson]

    I have an FPGA program that I've compiled and run on several sbRIO's. Recently, I was going to load a new sbRIO. Opened up the project. It won't compile! It says the SCTL misses its 24.99ns window by 0.07ns. I haven't changed the code since the last time it compiled. And not only did it use to compile, but it always ran just fine. One thing that I have changed in the interim is that I've installed more recent versions of LV. (This VI is in 2018, I've installed 2020 and 2021, with FPGA.) So I think it's quite likely that the Xilinx tools have been upgraded since it last compiled correctly. Is it possible that a new version of Xilinx would refuse to let it compile even though it ran just fine when compiled by an older version?

TIA,

    DaveT

[Jacobson-ni]

Things can change from version to version. It's possible that you were already pretty close to the 25ns requirement so some small change pushed you over.

If you're just looking to compile and won't be doing additional development you're probably close enough that you could try just running a few compilations to see if one works.

[crossrulz]

When I inherited a program that ran into this issue, the biggest thing that fixed my compile issues was to shrink a DMA FIFO (just went down to the next lower possible size).

The other trick that helped somewhat was to add Feedback Nodes in the middle of wire paths to add a form of pipeline.  This will add delays.  In a Single Cycle Timed Loop (SCTL), that delay is 1 clock cycle, which is usually bearable.

[Jacobson-ni]

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@crossrulz wrote:

When I inherited a program that ran into this issue, the biggest thing that fixed my compile issues was to shrink a DMA FIFO (just went down to the next lower possible size).

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Do you find this to be helpful even if there are plenty of overall resources remaining?