FPGA reference gets invalid

[TRanjith]

Hi,

i am taking the reference of FPGA VI in RT code.  passing it to sub VI. Sometimes i see link(wire) between FPGA reference and Sub VI is broke. What could be the reason? if i recreate the sub vi input it solves the problem.

Thank you,

Ranjith

[Baji]

If u do any changes in the FPGA code and complile,then ur FPGA reference will updated, but inside the subvis you placed the old reference controls only.so its showing broken arrow in all of your subvis.

[TRanjith]

I have many such references. how to overcome this problem?

[Baji]

Dont pass the reference directly to subvi, Use globals,queue or notifiers to pass the reference inside the Vis. Try this but i dont know its a correct solution.