FPGA simulation on Development computer - different results at different running time

[DatLe]

Hello,

I am using a Matlab program to save data into input text files, use Custom VI to read these input files into Labview FPGA simulation program as Analog Inputs. Do calculation and send result of my program into Analog Outputs, that is actually saving calculation result into output text files. Use Matlab to read data from these output text files and plot them. However, I see that even for consecutive running times of my simulation program, Labview gave different results, which I can see clearly by comparing with a reference result in Matlab. Has anyone seen this issue before and what could be the reason, solution? Btw, my program uses block memory, but I tried not to read and write to a same address of the same block memory simultaneously by using sequences.

Thanks,

D.

[altenbach]

How different are the results? Day&Night? Flicker in the LSB?

If the data goes through an analog step, I would probably expect some variations. Can you describe in more detail what you are seing? Maybe attach some comparison data. Is there a pattern?

Thanks!

[DatLe]

Two different running times are like after 5 seconds. (Time to plotting data in Matlab). However, if I run different times and connect (fake) Analog Input directly to Analog Output, the there is no variation in the result. That means the variation is due to calculation in the program somehow. I am attaching the result here. The red curves in 3 running time are for reference. You see 3 blue curves have different results. Before sending this data to Analog output, I already scaled up by 50 to reduce error due to resolution (value range for Analog output is +/- 16), and for the plots here, I scaled down by 50 to compare with the reference.

Thanks,

[Aldo_A]

Hi DatLe,

Thanks for posing the screenshots of the data variations. The next step here is to take a look at what your FPGA VI is calculating, can you give us some background? post screenshots/VIs? I would like to know what functions you are using that might be causing the variation. Thanks!

[DatLe]

Hi Aldo,

It's difficult for me to describe things. 

1) I am sharing the Labview folder Labview Simulation Issue.rar which is the Labview Project I am working on. It's pretty complicated although I tried to simplify it the most. Please uncompress, run pbsh.lvproj, right click "FPGA Target"->properties, under category, select Debugging, on VI Path of "Use Custom VI for FPGA I/O", please find and select the VI named "Custom VI for FPGA IO.vi" where you put this folder in your computer.

After that, please open FPGA_IO_estimator_simulation. Run it.

(Link: https://www.dropbox.com/s/r9yeogly4siczet/Labview%20Simulation%20Issue.rar)

2) After done with Labview running, please open the Matlab file "read_labview_issue.m" and change the variable "folder_path" to where you put the Labview folder and run it. You will see the result of Labview FPGA simulation+reference result (read from a file) plotted together. Save the plot.

(Link:https://www.dropbox.com/s/yppdcny9acwvx8i/read_labview_issue.m)

3) Repeat the step 1, step 2 many times, you will see that result from step 1 varies with each time of running.

Thanks,

D.