FPGA socketed CLIP over MIO Port on sbRIO

[Christian.B]

I'm trying to integrate a serial interface (RS232) on my sbRIO 9627 board. It is possible to generate the CLIP code via the generator in the project tree, but I'm missing the socket instance in the tree under the FPGA target.

1) Is there a possibility to make it visible on the tree?

My first attempt to overcome the limitation of the 96 RMC DIOs in the CLIP generator is, that I connected the RX and TX lines from the MDIO in the FPGA main.vi direcly to the RMC DIOs. The goal is to use the extra 4 DIO channels for serial ports (since the hardware is already done).

2) may this work and does anybody know if it is possible at all because I do not know if the buffers like each other?

thanks in advace,

Christian

[agnes88]

Hi Christian,

have you managed to solve this case? If so, could you share the solution at the forum, please? It could help others if they encounter a similar problem.

If not, perhaps one of those links would be helpful regarding the 1st question:

https://forums.ni.com/t5/Hardware-Developers-Community-NI/sbRIO-9651-SOM-IO-Interface-and-CLIP-Gener...
https://forums.ni.com/t5/Hardware-Developers-Community-NI/sb-RIO9651-socketed-CLIP/gpm-p/3737413?pro...

Let us know whether you worked the issue out (or the links above were helpful), if not I'll have a closer look at it.

[Christian.B]

It seems, that redirection of signals from or to the MIO connector from the RMC is not possible. 

1) A configuration via the CLIP generator has to incorporate all signals on the RMC port. This means, the FPGA target could only be programmed once. Either by a preset or a custom CLIP configuration.

2) Consequently, used I/Os for serial ports vanish in the available ports on the FPGA listing. And a link between MIO and RMC ports isn’t programmable in the FPGA vi.

It would be nice to have a routing matrix, where this could be done.