FPGA target compiling failed

[masterwho]

Hi all,

I met a problem when I tried to compile my FPGA target VI. The compiling failed for some reason halfway after the compiling started. I post some screen shots of the error information from the labview.

What may causes this problem? How could I fix it?

Thank you very much!

Kind regards,

masterwho

[dkfire]

as the compiler says, your program is too big to fit inside the FPGA.

Your program is using 151.6% of avalible Flip Flops, that is 51.6% too many.

You need a larger FPGA or redesign you program to use less Flip Flops / slices.

[masterwho]

Thank you very much for your reply. Could I ask that what do you mean by larger FPGA? Do you mean FIFO which has larger number of elements?

Thank you again!!

[dkfire]

No, not the FIFO's.You can get FPGA's in different sizes.

But one of the things you can do to reduce the amount of Flip Flops that your program is using, is to reduce the size of the FIFO's.

Try to figure out if all your FIFO's has the right size or if some can be reduced. 

[nathand]

If your FIFOs are memory-based, changing their size will not reduce your flip flop use.  However, if you are using logic-based FIFOs, you might be able to save space by reducing their size or changing them to memory-based.

By different-sized FPGAs we mean the number of gates; for example, NI lists some of their Virtex-II FPGA cards as 1M gates and others as 3M gates.

[dkfire · Accepted solution]

Also are you having large arrays on the front panel of the FPGA VI ?

Or are there large arrays inside the code ?

If you can, post a snipet of your code.

[masterwho]

Hello dkfire. Thanks very much for your help.

You are right. I used a too large array in my code. It works after I decrease the size of array.

Thank you very much!