FPGA timing issue at different sampling rates

[rschmeling]

I am monitoring the rotation of a disk that is spinning on an axel.  In this disk there is a hole milled into it and everytime the slit passes across a laser path the light is then detected with a photodiode.  I am rotating this disk ar roughly 83 Hz or 5k RPM. 

(Using PD Raw 2_ver1.1 on target side and PD Raw Test Front on the host)

When I collect the data at 200MHz I get a calculated value of the rotational speed to roughly 1180 Hz or 112000 RPM.  If I change the clock for the single cycle time loop to 40 MHz I calculate the rotation speed to be 444 Hz or 26600 RPM.  Both values obviously not the correct value.  The only changes I made between each test was changing the timing on the single cycle time loop and changed the sampling rate input to the Scale Data subVI on the host side to the corrisponding sampling rate.

In trying to test slower sampling rates it would not let me compile the VI saying that 'a loop using an external clock must never exit' (or something similar) I created PD Raw 2_ver1.2 and instead of using the time loop I used the loop timer function to acheive slower sampling rates.  Still using the same host VI, but changing the sampling rate input to the Scale Data subVI.  That gave me a more accurate value of 70 Hz or 4195 RPM (my motor screen reads 5k RPM but there is quite a bit of leway hence measuring using LV)

While I am anticipating some small changes in the calculated speed, since the motor is shut off during compliation and then restarted, I do not understand why I am seeing such large differences in my calculations. 

I have included in the folder the raw data before it passes through the Scale Data subVI as well as the data after the subVI.  When I manualy plot the data in Origin I take the leading edge of the first two peaks, subtract the time of the first from the second (convert to time by dividing by the sampling rate is looking at the raw data).  I then take the inverse to get the rotational speed. 

If anyone would be able to spread light on the why I am seeing what I am seeing I would greatly appreciate it.

Thank you,

Ryan

[Catherine-B]

Hi rschmeling,

Can you add some error handling on the FPGA side to see if the FIFO is timing out? At the faster loop rates, you may be overflowing the FIFO, which means you could be losing data points. 

[rschmeling]

Cathrine

If there were a timeout error wouldn't it throw an error window and pause the execution of the VI? 

I added the code shown in the screen shot to monitor if there was a data overflow.  In the ~15 times I tested it there was no data overflow observed. 

Ryan

[DylanDylanDylan]

Hi Ryan,

I In order to acquire lossless data from your AI you need to place the IO Node in a Single Cycle Timed Loop with the clock source of the loop being an IO Module Clock.

What CLIP are you using?

Do you use an external clock?

I would imagine the CLIP you need is the NI 5761 Single Sample CLIP (Right Click IO Module in the project). This will allow you to use the internal clock of the adapter module which is running at 250MHz. This means each cycle of your loop you will get one new sample from your analog input channels (you have access to 4 AI, 8 PFI in this CLIP). Right now it looks like you are grabbing data at a rate of 200MHz off of a clock generated from your 40MHz FPGA clock which is not routed to your Adapter Module (which is likely acquiring at 250MHz depending on CLIP you chose) so you lose data which gives you bad RPM measurements.

I highly suggest going through the examples found in the LabVIEW example finder for the 5761 (NI 5761 Single Sample CLIP) as this shows the proper way to read data from the adapter module and you can then modify that code to meet your needs (make a copy so you don't overwrite the original example).

Regards,

DylanC