Facing problem while taking 1MHz clock on PFI in 9205 in 9154 chassis.

[monualone]

HI,

I am using 9205 boards on 9154 MXI express RIO. I have configured the PFI channel for the datation of the sample for which I'm using 1MHz external clock. In this I'm facing two problems while running it in FPGA mode:

1. The 9205 ports scanning giving me error if I use the single time loop working on 40MHz internal clock, but works OK in a while loop.

2. If I run it using a while loop (with 1microsecond loop time) with the external 1MHz clock, it's not working as desired infact the clock reading is not continous, while runnig with an internal clock working fine. Unable to understand it. 

Please helo me out.

Thanks

[Jacobson-ni]

As far as your first question goes, you cannot have an analog input inside of a single cycle timed loop because it takes more than 1 clock tick to execute.

http://digital.ni.com/public.nsf/allkb/722A9451AE4E23A586257212007DC5FD

In regards to your second question, I am not really sure what is going on. Can you attach a VI or snippet of your code and under what conditions it works and does not work?

[monualone]

Hi Matt,

Thanks for your reply. With respect to your answer for my first point, I would like to tell you that the single cycle timed loop I'm using here is not for AI but for PFI.

For the second question, so here I'm attaching the vi for your reference. The explanation is as follows:

1. I've to use four 9205 for acquiring 122 channels at 1KHz.

2. The acusition will be time stamp using 1MHz external clock, which I've connected to one of the 9205 board's PFI, named MHz Chrono.

3. The acquisition will start with an external trigger. This external trigger, I've connected to the second 9205 PFI, named External Trigger.

4. The sampling clock is also external, so I conected it to the third 9205 PFI, named Extenal Samling Clock.

Now the problem is coming, when I'm using the 1MHz external clock, this isn't working properly not even with the while loop.

Another problem I faced yesterday itself.  I inserted one more 9205 board in 9154 chassis and compiled the code. The problem is, if I make seperate FPGA I/O node for the boards it gives me the memory error however putting all the channels in a single node like in the vi attached, it compiled without any error, what's the reason behind this behavior I'm unable to understand? 

Hey by the way can you please help me out in one more matter. The point is if I wanna use the same 1MHz clock for the sampling also by decimating it to 1KHz, how can I do this?

[monualone]

Hi Matt, 

Have you got any solution to my problem.