Fast datalogging using the FPGA?

[ghp_1]

Hi

I am trying to determine how I can log data with a sample rate in the microsecond range from an analog measurement on the CompactRIO

Is it possible to achieve this by transfering the measurements and measurement time from the FPGA to a host VI through a FIFO?

The reason for the question is that the cRIO CPU nor host PC can run VI's at a microsecond sample rate, so how can this be achieved without data loss?

Thanks!

[Jacobson-ni]

You place elements into the FIFO on your FPGA point by point but on your RT or Host VI you will need to take multiple elements from the FIFO every iteration or you will fall behind like you described. The cRIO developers guide explains this and shows some good examples starting around page 90.

https://www.ni.com/en/shop/compactrio/compactrio-developers-guide.html

[ghp_1]

Hi

I've been trying to reproduce the example shown on p. 94, however for the case structures the code is only shown for one case (false or true)

The text under the figure refers to a VI, do you know of these are available for download somewhere?

Thanks

[Sam_Sharp]

In chapter 13 (pg 251), they discuss the sample projects that are referenced in the guide - does that help?

[ghp_1]

Didn't help but thanks for the suggestion

I've also been trying to use the following two articles:

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000x0UdCAI&l=en-US
https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/designing-a-host-vi-to-read-data-in-dm...

However both the above two articles lack a way to empty the FIFO once it gets full (which naturally happens whenever the application starts because the the FPGA and host VI doesn't start exactly at the same time) so the program just stops

Any suggestions for a complete example that actually works?

Thanks!

[Sam_Sharp]

To empty the FIFO, just read all of the elements when your application starts and discard them. You can also 'stop' and then 'start' the FIFO using the appropriate methods which will delete all data from the host memory and FPGA parts of the FIFO.

There are Streaming DMA examples in the LabVIEW example finder.