Faster FPGA analog input

[anonymus]

I am trying to convert a 2Vpp sine wave at 1Khz into a square wave at 1Mhz. 

 I am using a RIO FPGA PCI board with a function generator as my sine wave source. 

My problem is that Labview will not let me use a FPGA analog input in a timed loop, I must use a while loop to read the sine wave.  The while loop is not consistent enough in timing accuracy. 

Is there another way to read in an analog input faster?

[Spectre_Dave]

Use the loop Timer function inside the loop.

[Pcorcs]

Analog input on PCI R-Series devices are specified per the User Guide and Specifications. The FPGA loop rate at the 40 MHz base clock level over samples the Analog to Digital converter built into the board. Each time the AI task is called it will take a minimum time to send a request for data to the ADC, and recieve it on the FPGA. For example, the sample rate specified for the 7831R is 200 kHz per channel. Regardless of the Top-Level clock rate, the AI task will take a minimum 5 us to complete, each iteration. 

Remember, FPGA programs, once compiled will maintain deterministic execution (with the exeception of blocking funtions). The while loop placed wihtout timing defined will run on the Master Time Base of 40 MHz, meaning that each function's 'tick' duration will be based on the 40 MHz time base. The use of case structures may induce different code paths, which would inherently cause the While Loop to iterate at different rates. A While Loop, with no blocking functions and no case implementation, will run at a constant rate once compiled. This behavior may be benchmarked using sequence structures.

What type if inconsistency are you experiencing in your application?

PCorcs