Hello All,
I am currently working on a control systems project which requires synchronization between digital and analog signal generation, where certain analog signals are output as Ramping signals. Currently, I have created the programming for microsecond digital control, and I am able to synchronize analog generation by dedicating a digital line from the PCI-6229 board as a sample clock for a changing analog voltage. To achieve this I hardwired a line from digital output 31 of the 6229 board, and ran it to the PFI 1 line of the 6711 board. This method does allow for step changes of the voltages everytime the digital line goes low. So essentially, I am able to create the digital signals I need, as well as change analog values in a one edge step. However, there will be certain parts of the experiment which require the analog voltage change be slowed down slightly, with the use of the ramping function vi. This means that instead of changing the analog values in large steps, the program needs to write an array with many small steps between one voltage and the next, and then use a much faster sample clock to output the values.
My solution for this is to use an analog counter, which is triggered by a different digital line, to create a finite pulse train with a frequency of 10kHz, that will put out as many samples as the timing file designates. This 10kHz signal is then hardwired into the same PFI line that was set to receive digital output 31. This means that the PFI line will receive either a very slow clock from the changing digital line, or a very fast clock from the triggered 10kHz.
My first question is, will it potenitally damage the board if say the PFI line received 2 high signals at once? If we are careful with our data setup this should not happen.
Secondly, in the program I have attached, I am able to make the counter output a 10kHz signal, but only when the implicit clock is set to continuous samples, and in this case the 10kHz train does not stop unitl I end the program, I have looked at the example Gen Dig Pulse Train-Finite-Retriggerable, where I am able to make a 10kHz signal that only lasts for x amount of time, and the only difference I can see between my program and the example is the location of the start task vi.
