03-05-2012 12:20 PM
Hello,
I have to make an application capable of reading and writing (nor at the same time) data at a rate of 5MHz of 2 analog channels and 3 digital lines.
I have made an application that can read using U64 DMA FIFO and then unpack the data to the above channels - this is working fine and fast enough, yet it does not the opposite way. I have tried splitting the data using two DMA channels (U32 and U8) still with no luck.
I have made the FIFO's to never arbitrate and put it all in a very small vi that only read DMA yet no luck.
I have to know if the hardware can support such speed and why does it work to one direction and doesn't on the other.
Attached are two VI's - FPGA FIFO read and RT FIFO write.
My setup:
PXIe 1071 chassis
PXIe-8100 controller
FlexRIO 7952R
RFtranciever module NI5781R
Labview 2011
Thanks,
Yuval Yohai,
CTO & Test System Integrator
TestVIEW Ltd.
03-16-2012 03:50 PM
Hi Yuval,
What specific hardware are you using? Is this on a PXI system or a desktop computer? What operating system are you using? Can you clarify what behavior you are seeing when your FIFOs are not working.
Regards,
Josh B