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FlexRIO sampling points slip between runnings

Hi guys,

 

I got NI 7972 FlexRIO card running under 100MHz data clock. The data generation and acquisition is in the same SCTL. 

Now I am doing IQ sampling on a 25MHz signal. Here is my problem: between each running of FlexRIO, the first sampling point slips and it results that my phase calculation arctan(I/Q) randomly selected between 4 values. Any idea to solve this? 

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More to add, I am using PXI backplane as ref clock in. The 25MHz signal is also generated from FlexRIO. 

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Which FlexRIO Adapter Module (FAM) is connected to the 7972?


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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It is Ni 5783

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@zyb1003 wrote:

It is Ni 5783


Which clock is driving the SCTL?


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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