Frequency scaling down of the signal

[Navin4561]

Dear all,

i am trying to send out the generated sine wave with freq 1kHz @ fs 3MHz by using AO 0 channel of the NI5781 FPGA interface module and observing signal on CRO, the signal freq is showing 33KHz.

it is always coming output signal frequency  33 times of the input signal frequency.

i was trying so much, still i could not able to fix it.

i am attaching the vi below for your reference.

so im eagerly waiting for your valuable response.

Regards

Navin 

[cbutcher]

Assuming your FPGA code successfully compiles, you'll get one output value per channel per "IO Module Clock 1" period.

Since we don't have your project file, I have no idea what that might be.

If you're using the AI loop at the top of the VI as a method of viewing the output, then this will produce data at a rate of 1/"IO Module Clock 0" period.

Since both clocks probably give their rate as a frequency (i.e. MHz, kHz, etc) you can read those derived clock values to find out the expected rate.

The rate on the RT system, as calculated by the Single Tone Information, will have no effect whatsoever on the rates you acquire/output data from the FPGA with this system.

[GerdW]

Hi Navin,

unfortunately you forgot to attach your project file…

How did you define the clock used for that SCTL?

[Navin4561]

Hi 

thank you for your response

please find the project file for your reference

Thankls

[Navin4561]

Hi cbutcher,

please find the project file for your reference

[GerdW]

Hi Navin,

no need to post that ZIP file twice…

I still cannot find that "IO Module Clock 1" in the project, there is only "IO Module Clock 0" visible:

So the question remains: how did you define that clock used for the SCTL?

[Navin4561]

Hi GerdW,

i am using the internal generated clock with 100MHz for both the clocks ("IO Module clock0" and IO Module clock1")

i have included the both the clocks "IO Module clock0" and IO Module clock1" . still output signal frequency on CRO is 33 time of input signal frequency.( input signal 1KHz and Output signal getting is 33KHz)

[Navin4561]

"So the question remains: how did you define that clock used for the SCTL?"

i have used "FPGA base clock" to define SCTL.

[GerdW]

Hi Navin,

the AO loop is driven by clock1, so it doesn't help to show the properties of clock0…

The waveform in your "sine_test" VI is created using a sample rate of 3MHz: when Clock1 also runs at 100MHz then there is your factor of ~33!

(Unfortunately I cannot check all items in the project tree, probably because I didn't install PXI support with LabVIEW.)

[Navin4561]

Hi GerdW,

thank you very much for your response.

i have made sampling frequency of the sine wave is 3MHz and clock1 frequency is 3MHz, even though i am getting the output signal frequency on CRO by a factor of 33.

what might be the issue can any one please suggest me.

regards

navin