Generate IRQ on cRIO fpga from digital input line

[jeb99]

I'm a beginner.  I want to generate an interrupt using a cRIO 9076 fpga when bit 17 of an input ni9403 module goes true.  The interrupt would connect to a subVI (?) which would read multiple u16 words and put them in a dma fifo to be transmitted to the host pc.  The subVI would then re-enable and restore the interrupt.  We plan a similar interrupt-driven subVI to transfer data in the other direction.  We've already managed to transfer data in both directions from the cRIO/fpga to the equipment on the non-host end as a test.

jeb99

[nathand]

The only interrupts in FPGA are for signaling the host. Fortunately you don't need an interrupt to do what you want. Just set up a while loop that checks the digital line continuously. When it goes true (or false, as appropriate), stop the while loop and proceed to read the data into the DMA FIFO. Then, if necessary, add another while loop that waits until the digital line returns to its normal state. While flat sequence structures are not usually good practice in LabVIEW, they're OK in FPGA. You could use one here with three frames - one for the loop that waits for the digital input, a second that puts data in the FIFO, and a third that waits for they line to reset. Put the sequence inside a bigger while loop and you're done.

[jeb99]

Is it possible to have 2 while loops executing at the same time in the fpga?  We have 2 entities transmitting to the cRIO/fpga at the same time,  the equipment to fpga to host and the host to fpga to equipment.

[nathand]

Yes, that's one of the major benefits of FPGA - operations can execute truly in parallel. Remember, the FPGA is hardware - it's a custom-designed processor that does exactly what your code specifies. It's not like your PC where a general-purpose processor fetches an instruction and executes it . On the FPGA there's no fetch and no instructions, the code IS the hardware. If you have two loops in parallel on the FPGA that don't share any resources, then those two loops are completely independent.

[jeb99]

Thank you for your help.  One more question:   If the 2 "independent" while loops shared a subVI, would the subVI be re-entrant?

[nathand]

Depends on whether or not you configure the subVI to be reentrant, in VI Properties->Execution. FPGA VIs default to reentrant execution, if I'm not mistaken. You probably want the subVI to be reentrant unless you're using it to pass data between the loops, but on FPGA that adds overhead for arbitration and there are better ways to share data (registers, FIFOs, memory blocks).