Global Variables in FPGA module - timing

[sskr33]

Hi!

Let us say we have two loops, A and B, running in parallel on FPGA. The loop A acquires data and sends it to the loop B. Loop A uses Loop Timer in a flat sequence to execute the loop every 1 ms. It takes the acquisition algorithm in loop A 100 us to get the data and for the data to reach global variable input.

My question is: is the data sent through the Global Variable right after it reaches the input (after 100 us), or after the Loop Timer expires (after 1 ms)? Is the data from loop A available in loop B after 100 us or after 1 ms?

[wiebe@CARYA · Accepted solution]

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@sskr33 wrote:

Hi!

Let us say we have two loops, A and B, running in parallel on FPGA. The loop A acquires data and sends it to the loop B. Loop A uses Loop Timer in a flat sequence to execute the loop every 1 ms. It takes the acquisition algorithm in loop A 100 us to get the data and for the data to reach global variable input.

My question is: is the data sent through the Global Variable right after it reaches the input (after 100 us), or after the Loop Timer expires (after 1 ms)? Is the data from loop A available in loop B after 100 us or after 1 ms?

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Global variables don't send data. They have a value, that can be read\written.

The time it is written has little to do with the loop timer. The value is set when it's wire receives the data. If the wait is forced before the write, it's at the end of the iteration. If it's written in parallel to the wait, it's probably more at the beginning.

Sounds to me a global is not the optimal solution (it often isn't), but there's not enough info to go on.

[Intaris]

If the loops are running at different rates, there will be

a) fabric overhead with each clock domain crossing (CDC) costing (x*)+12 registers

b) a time delay which is a certain number of clock cycles depending on the relative clocks fo the two loops

c) lost data if you're expecting this to be written to and read from each iteration of the loops (see HERE where I ran into exactly this problem)

The LabVIEW FPGA compiler basically implements a CDC global as an FPGA Handshake primitive.  A Global without CDC is simply a Register.

What are your requirements?