HDL Node - How to import existing VHDL code

[Emmanuelol]

Hi, yes i read before the links about use external files, but my doubt is for example a use code before mentioned in a vhd file wich i added to hdl node interface, i defined inputs and outs but the program show in the error list two errors, one of this is enable chain not handled, and out no handled, also part of my confused, is you add vhd files or other type of file builded for ISE xilinx?, because in the example in how use the hdl node your use ISE xilinx for extract other file from vhd file maybe i am not understood fine, well for the moment thanks for any help can yo give me.

[mishkin]

Emmanuelol,

Make sure you're handling the enable chain correctly. Read the passge below for more details, but it sounds like you're not asserting the "enable out" chain output in your HDL code when it's done. Make sure it is done in the code in order to pass data flow control back to Labview after your code executes. 

"Meeting the Requirements of Using the HDL Interface Node with the LabVIEW FPGA Module

LabVIEW and the LabVIEW FPGA Module follow a data flow model for running VIs. A block diagram node only executes when all its inputs are available. When a node completes execution, it supplies data to its output terminals and passes the output data to the next node in the data flow path. The HDL Interface Node uses an enable chain to follow the LabVIEW data flow model. The enable chain is the collection of signals and an associated protocol for controlling data flow of inputs and outputs of the HDL components. The HDL Interface Node includes the following execution control and enable chain signals as default ports, listed on the Code tab.

Enable Chain Inputs

• enable_in—The signal LabVIEW asserts when all inputs wired to the HDL Interface Node are valid. LabVIEW asserts enable_in when all the nodes before the HDL Interface Node in the data flow finish executing. You can monitor enable_in to know when the HDL code can start executing.
• enable_clr—The signal the VI or loop asserts to indicate to the subVIs or nodes, including HDL Interface Nodes, in the VI or loop that they must deassert enable_out on the next rising edge of clk. In loops other than the single-cycle Timed Loop, enable_clr asserts after each loop iteration is complete and before the next iteration begins. If you use a single-cycle Timed Loop, the VI or loop does not assert enable_clr.

Enable Chain Output

• enable_out—Assert this signal in the HDL code when you want to indicate to the block diagram that the HDL code is complete and to signal to subsequent functions in the data flow to execute.

The HDL code you include in the FPGA VI must fit into LabVIEW data flow execution semantics by properly controlling the enable chain. If you do not properly control the enable chain, the HDL Interface Node might disrupt the execution of the other nodes on the block diagram. "

[Emmanuelol]

i'm learned how use hdl node texting the code, but i have a doubt in how use for example vhd codes,wich i divide in module, using component and port map??

[prashiit]

Hi everybody,

       Any body please let me know whether HDL node interface supports verilog HDL or it only suppports VHDL

Thanks

Prasha

[Anna_K.]

Yes Verilog HDL is supported by the node.

Thanks,

Anna K.

[Kalyansuman]

HI All,

Here i have some quiries in using the HDL node.

Trail 1:

I had a design for Filter using a VHDL code, i had added the same using the external source tab to HDL node, then

it had inferred the memories used in code in the report.  The design is preforming as expected.

Trail 2:

In this trail instead of adding the  VHDL code, i tried adding the ngc files from ISE to the hdlnode, here the memories(block ram) are not inferred in the   synthesis report generated by labview.

Can some one suggest me, how to use the ngc files efficiently.,

Note: while generating the ngc files in Xilinx ISE tool, i had removed the add I/O Buffers.

Regards

KalyanSuman

[Robbob]

Kalvan,

What do you mean by the memory was inferred?

Does the code implemented in netlists run at all?

Maybe if you can post your code or at least the compilation report, we can take a closer look at it.

[Kalyansuman]

Dear Robbob,

Thanks a lot for the reply.

the problem which i wrote in my previous post got solved.. anyways  I will explain the problem i had faced in detail.

1. I had written a verilog RTL for a small FIR Filter(Having 1 RAM and 1 ROM). 

2. Created a .ngc file using Xilinx ISE.(ex filter.ngc)

3. In the Labview environment, using the above ngc file and hdlnode the VI is executed.

4. Observed the reports generated by Xilinx ISE and Labview.

5. The synthesis report generated by the ISE is showing the RAM and ROM, where as the synthesis report generated by Labview is not showing the same.

Solved the above problem:

1. Since i have used the ngc file, the labview report is not showing that memories in the synthesis report, however the same memories are reflected 

      after mapping.

One more question, is it possible to use the verilog RTL directly in the HDL Node instead of VHDL RTL or NGC/EDIF files 

Thanks&Regards

Kalyan Suman