HDSIO 6547 - Output signal frequency different from Sample Clock frequency

[NivethaShivan]

Hello,

I am generating digital output signals using niHSDIO 6547. I have the HSDIO connected to a NI CB/SCB 2162 board and obtain the output signal from dut0 on the scope. The frequency of the clock signal I am using is 100MHz, but the output signal has a frequency of only 50MHz. I am not sure why this is happening.  

Could someone please help me! 

Thanks. 

[Lea_D]

Hi NivethaShivan,

You might get a better response from other forum users if you post in the Digital I/O forum forum instead of the LabVIEW forum. This way other digital I/O users might be able to help out as well. If you do decide to do this though, please be sure to cross reference both posts with a link to the other one.

In regards to this issue though, I'm wondering if you're using a LabVIEW example to do this or just testing with test panels? Also how are you testing what the output frequency actually is? This might be a situation where posting a picture of your code could be helpful. The specifications manual  says the device will go to 100MHz maximum. All the other values would be divded down from this number, so I'm fairly sure that somehow, the number is just getting divided down  by 2 somewhere in there. 

If you are using your own code for this, I would suggest starting with one of the examples. You can get to these examples in LabVIEW by goign to Help » Find Examples... This will open up another window called the NI Example finder. In the middle of this, there will be several folders. Navigate to Hardware Input and Output » Modular Instruments » NI-HSDIO. I would suggest using the Dynamic Generation and Acquisition demo located in the demos folder.

Hope this helps!

[Lea_D]

Hey Nivetha,

After speaking with some people over here about this device, I wanted to give you a more complete answer. the 6547 card actually isn't capible of doing the divide-by-N, so that's not what you're seeing. What you're seeing is actually the toggle rate and not the clock rate. Basically, the clock rate is set to the maximum (100MHz), and the clock rate is the frequency that the value is updated on a channel. The toggle rate is the frequency of the generated signal that you're seeing. The maximum toggle rate is going to be half of the maximum clock rate.

However, you can use the niHSDIO Export Signal.vi to export the sample clock into one of the PFI lines, DDC CLK OUT, or CLK OUT. This will allow you to use the 100MHz clock signal. 

An advanced functionality of the 6547 is the 200Mbps in double data rate mode. This clocks on the rising and falling edges of the 100 MHz clock rate allowing you to get the 100MHz signal. You can set this up in the software.

Hope this helps a bit more than the first post,