HOST to FPGA DMA and block memory

[Sr-QH]

Hi

I am trying to transfer data from the HOST VI to the FPGA VI using FIFOs DMA and then transfer these values to block memory on the FPGA on a SBRIO9632. I understand there are alot of examples in the examples folder in Labview and also on this forum, but I have not been able to solve the problems in my script using them. I would really appreciate some help.

On the HOST VI, I am writing two arrays to two different DMA FIFOs and then in the FPGA VI I am transferring this data from the FIFOs to the block memory, and then outputting the block memory values to the analog output channels. Unfortunately I am not been able to see an outputs from the channel and I'm not sure how I can check whether the data is being written to the FIFO and the block memory. Please see the attached files below. 

[crossrulz]

Personally, I wouldn't use the block memory.  I would just read the FIFOs and directly wire them to your output and time delay.  This would eliminate your sequence structure and only having the one loop.

[Sr-QH]

Ok thanks for the advice, I can't seem to read out all the values from the FIFO. I am writing an array from the HOST but when I try to read it on the FPGA, I can only read the first value. I have attached a simpler VI, could you please tell me if there are any structural errors in the HOST VI.

[Terry_ALE]

That's how FIFOs work.  You have to keep reading from the FIFO until it is empty or your have all the values you need.

[crossrulz]

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@Sr-QH wrote:

I am writing an array from the HOST but when I try to read it on the FPGA, I can only read the first value.

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Yes, exactly.  You might have noticed, but you were doing the same thing with your old code as well (reading 1 memory location at a time).  After all, you can only write 1 value to the output at a time.  Of course, now you are missing the time delay in your FPGA loop in order to get the update rate you want.  Also, I would remove the first While loop (as well as the sequence structure) and the "Timeout" input on the FIFO Read.  This will cause the output to only update when there is a value in the FIFO.  There isn't even a reason to look at the Timeout indicator.

[Sr-QH]

Thanks for your response, I really appreciate your help. I would like to explain my aim, so that perhaps you could advise me better. I am looking to transfer one array of values to the FPGA to be output on the analog channel but also transfer a second array to set the time period for that output value. e.g 1st value of 10V for 1.25 ms and next value for 5V for 2.5ms. I can't map these from the HOST VI as the timer on the HOST VI uses a ms timer. Could you please advise me on how I can set the timer period between each read of the FIFO element on the FPGA. I hyave tried the FPGA VI attached however the output immediately goes to the last value